From patchwork Sun Jul 21 17:49:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 18459 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f71.google.com (mail-qa0-f71.google.com [209.85.216.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A25B125DFC for ; Sun, 21 Jul 2013 17:49:52 +0000 (UTC) Received: by mail-qa0-f71.google.com with SMTP id bq6sf1088262qab.2 for ; Sun, 21 Jul 2013 10:49:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=eyGmRGd9YRgJJ1wGM94nnDo2ahaBKtzrdLKkTaqJ9As=; b=pWIHH5OSMkDXeNW7p1hQx5dGesZVvBEUrKIxB8Icw/56fAXfQpgndkADPSs3/Mpf+y kD4dA56zn9elWh1lqwCTCAaADg1f0jvxOTukJgWztWpOHMfZEsiq502kbiNOZz1gPsIS r9lcotG6G5PCF2/S+MOpQzgTc0Ity3U8opRWwG1XM3rEBeezvKKlenQXTC4lUu7myrQq x14JMarSUKwF3qWk+VkhkTD3aehddEg+yH6NwD8PwVBqzYrp2YR2uCi8GiMY7hvxsi4i uJEX8iOBAk9ZThd3SlDDVYDKf4fETeo48rxkf4dmFX2bSyIBHlMrPkL+1Kwnfx3Hc248 6zhQ== X-Received: by 10.236.74.169 with SMTP id x29mr14046120yhd.34.1374428991755; Sun, 21 Jul 2013 10:49:51 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.37.229 with SMTP id b5ls2491273qek.18.gmail; Sun, 21 Jul 2013 10:49:51 -0700 (PDT) X-Received: by 10.220.167.2 with SMTP id o2mr4185884vcy.61.1374428991465; Sun, 21 Jul 2013 10:49:51 -0700 (PDT) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by mx.google.com with ESMTPS id cx7si6080695vcb.121.2013.07.21.10.49.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 21 Jul 2013 10:49:51 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.180; Received: by mail-ve0-f180.google.com with SMTP id pa12so4494303veb.25 for ; Sun, 21 Jul 2013 10:49:51 -0700 (PDT) X-Received: by 10.220.83.69 with SMTP id e5mr5731096vcl.53.1374428991319; Sun, 21 Jul 2013 10:49:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.165.8 with SMTP id yu8csp23975veb; Sun, 21 Jul 2013 10:49:50 -0700 (PDT) X-Received: by 10.152.4.232 with SMTP id n8mr11147504lan.29.1374428989509; Sun, 21 Jul 2013 10:49:49 -0700 (PDT) Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com [209.85.217.171]) by mx.google.com with ESMTPS id v7si10647072laa.174.2013.07.21.10.49.48 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 21 Jul 2013 10:49:49 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.217.171 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.217.171; Received: by mail-lb0-f171.google.com with SMTP id 13so4701993lba.16 for ; Sun, 21 Jul 2013 10:49:48 -0700 (PDT) X-Received: by 10.152.25.135 with SMTP id c7mr10957235lag.39.1374428988411; Sun, 21 Jul 2013 10:49:48 -0700 (PDT) Received: from localhost.localdomain (c83-249-208-126.bredband.comhem.se. [83.249.208.126]) by mx.google.com with ESMTPSA id c4sm9686390lae.7.2013.07.21.10.49.46 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 21 Jul 2013 10:49:47 -0700 (PDT) From: Linus Walleij To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Stephen Warren , Anmar Oueja , Linus Walleij , Rob Landley Subject: [PATCH v3] pinctrl: elaborate a bit on arrangements in doc Date: Sun, 21 Jul 2013 19:49:40 +0200 Message-Id: <1374428980-3997-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.1.4 X-Gm-Message-State: ALoCoQn/votkMzzRssnXNqWwtnZrBdYCi5ac1diX9PBtH0FnT9uA8VAE429Zap8/1xs6xQKRgPvu X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This elaborates a bit on the pin control and pin muxing logic vs GPIO arangements in the hardware. Inspired by some drawings in a mail from Christian Ruppert. Both arrangements are confirmed to exist in practice. Cc: Rob Landley Reviewed-by: Christian Ruppert Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Updated with lots of good input and rewording from Stephen Warren. ChangeLog v1->v2: - Cut down to two arrangements that I *know* exist in reality. - Reword, rehash, rinse, repeat... --- Documentation/pinctrl.txt | 91 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 6 deletions(-) diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 052e13a..d2d7fc0 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -795,18 +795,97 @@ special GPIO-handler is registered. GPIO mode pitfalls ================== -Sometime the developer may be confused by a datasheet talking about a pin -being possible to set into "GPIO mode". It appears that what hardware -engineers mean with "GPIO mode" is not necessarily the use case that is -implied in the kernel interface : a pin that you grab from -kernel code and then either listen for input or drive high/low to -assert/deassert some external line. +Due to the naming conventions used by hardware engineers, where "GPIO" +is taken to mean different things than what the kernel does, the developer +may be confused by a datasheet talking about a pin being possible to set +into "GPIO mode". It appears that what hardware engineers mean with +"GPIO mode" is not necessarily the use case that is implied in the kernel +interface : a pin that you grab from kernel code and then +either listen for input or drive high/low to assert/deassert some +external line. Rather hardware engineers think that "GPIO mode" means that you can software-control a few electrical properties of the pin that you would not be able to control if the pin was in some other mode, such as muxed in for a device. +The GPIO portions of a pin and its relation to a certain pin controller +configuration and muxing logic can be constructed in several ways. Here +are two examples: + +(A) + pin config + logic regs + | +- SPI + Physical pins --- pad --- pinmux -+- I2C + | +- mmc + | +- GPIO + pin + multiplex + logic regs + +Here some electrical properties of the pin can be configured no matter +whether the pin is used for GPIO or not. If you multiplex a GPIO onto a +pin, you can also drive it high/low from "GPIO" registers. +Alternatively, the pin can be controlled by a certain peripheral, while +still applying desired pin config properties. GPIO functionality is thus +orthogonal to any other device using the pin. + +In this arrangement the registers for the GPIO portions of the pin controller, +or the registers for the GPIO hardware module are likely to reside in a +separate memory range only intended for GPIO driving, and the register +range dealing with pin config and pin multiplexing get placed into a +different memory range and a separate section of the data sheet. + +(B) + + pin config + logic regs + | +- SPI + Physical pins --- pad --- pinmux -+- I2C + | | +- mmc + | | + GPIO pin + multiplex + logic regs + +In this arrangement, the GPIO functionality can always be enabled, such that +e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is +pulsed out. It is likely possible to disrupt the traffic on the pin by doing +wrong things on the GPIO block, as it is never really disconnected. It is +possible that the GPIO, pin config and pin multiplex registers are placed into +the same memory range and the same section of the data sheet, although that +need not be the case. + +From a kernel point of view, however, these are different aspects of the +hardware and shall be put into different subsystems: + +- Registers (or fields within registers) that control electrical + properties of the pin such as biasing and drive strength should be + exposed through the pinctrl subsystem, as "pin configuration" settings. + +- Registers (or fields within registers) that control muxing of signals + from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should + be exposed through the pinctrl subssytem, as mux functions. + +- Registers (or fields within registers) that control GPIO functionality + such as setting a GPIO's output value, reading a GPIO's input value, or + setting GPIO pin direction should be exposed through the GPIO subsystem, + and if they also support interrupt capabilities, through the irqchip + abstraction. + +Depending on the exact HW register design, some functions exposed by the +GPIO subsystem may call into the pinctrl subsystem in order to +co-ordinate register settings across HW modules. In particular, this may +be needed for HW with separate GPIO and pin controller HW modules, where +e.g. GPIO direction is determined by a register in the pin controller HW +module rather than the GPIO HW module. + +Electrical properties of the pin such as biasing and drive strength +may be placed at some pin-specific register in all cases or as part +of the GPIO register in case (B) especially. This doesn't mean that such +properties necessarily pertain to what the Linux kernel calls "GPIO". + Example: a pin is usually muxed in to be used as a UART TX line. But during system sleep, we need to put this pin into "GPIO mode" and ground it.