From patchwork Thu Jun 20 10:47:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 18019 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f197.google.com (mail-qc0-f197.google.com [209.85.216.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 740102397B for ; Thu, 20 Jun 2013 11:03:03 +0000 (UTC) Received: by mail-qc0-f197.google.com with SMTP id u12sf8227823qcx.4 for ; Thu, 20 Jun 2013 04:03:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=sVEO4YnGJv9dRh9yCxTXchyyozSVYA+b/p5uRzGpxTA=; b=ELwHzXoQ8kVtfYW2x0Bd7p2SGF+bWesJXzWxEev1LXD8IRBoxm8hieS/D0KDcRvNxM aDDXigrJmjEk4+N3bbG0dRLO8PPFMRPaG2CyCM74Ya64O6Z/ZiW9RX/DR/Sh3geKRQ8i atq+ZXLZ5DxFlJ6XbLqoOCZkP655xR7IJ0nUvbWyYsjWJXwnrk2R2Td4TdGbG256AdGS jEpV5cKbDwx9WSykXHaewzoe8Wo40qFR1CHzEUwntNE3RDRDMKtegA/YPHutcY66ngeq wUHlyAAYcx6YinIB2qnnvssqZzOt5ZcrcktMyuSfspqAfloNBM7CVeMXoPb0E1M05q19 KT4w== X-Received: by 10.236.111.40 with SMTP id v28mr3987011yhg.27.1371726183283; Thu, 20 Jun 2013 04:03:03 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.132.197 with SMTP id ow5ls617422qeb.97.gmail; Thu, 20 Jun 2013 04:03:03 -0700 (PDT) X-Received: by 10.58.118.200 with SMTP id ko8mr2681979veb.94.1371726183064; Thu, 20 Jun 2013 04:03:03 -0700 (PDT) Received: from mail-vb0-x22e.google.com (mail-vb0-x22e.google.com [2607:f8b0:400c:c02::22e]) by mx.google.com with ESMTPS id ek9si804270vdb.89.2013.06.20.04.03.03 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Jun 2013 04:03:03 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::22e; Received: by mail-vb0-f46.google.com with SMTP id 10so4598881vbe.33 for ; Thu, 20 Jun 2013 04:03:03 -0700 (PDT) X-Received: by 10.220.53.7 with SMTP id k7mr2389039vcg.52.1371726182949; Thu, 20 Jun 2013 04:03:02 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.165.8 with SMTP id yu8csp16251veb; Thu, 20 Jun 2013 04:03:02 -0700 (PDT) X-Received: by 10.68.60.133 with SMTP id h5mr7082496pbr.15.1371726181908; Thu, 20 Jun 2013 04:03:01 -0700 (PDT) Received: from mail-pa0-x232.google.com (mail-pa0-x232.google.com [2607:f8b0:400e:c03::232]) by mx.google.com with ESMTPS id ad8si13255351pbd.186.2013.06.20.04.03.01 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Jun 2013 04:03:01 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c03::232 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=2607:f8b0:400e:c03::232; Received: by mail-pa0-f50.google.com with SMTP id fb1so6118132pad.23 for ; Thu, 20 Jun 2013 04:03:01 -0700 (PDT) X-Received: by 10.68.141.14 with SMTP id rk14mr7123565pbb.1.1371726181498; Thu, 20 Jun 2013 04:03:01 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id ri8sm27375631pbc.3.2013.06.20.04.02.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Jun 2013 04:03:00 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, patches@linaro.org Subject: [PATCH v2 2/2] clk: exynos4: Fix clock aliases for cpufreq related clocks Date: Thu, 20 Jun 2013 16:17:18 +0530 Message-Id: <1371725238-25437-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371725238-25437-1-git-send-email-tushar.behera@linaro.org> References: <1371725238-25437-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQl2nF16ZzgxWJAA5yVnjocPIHDwtf5cfmy/RWML2U1X5v453LzRI7F8QgcHZexwHGRlTyfr X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. Clock alias modifications for EXYNOS4 specific clocks are as below. Alias for clock 'arm_clk' is 'armclk'. Alias for clock 'mout_apll' is 'mout_apll'. Alias for clock 'mout_core' is 'moutcore'. For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'. For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'. Some of the clock aliases are newly defined and some are fixed up. While at it, also modify the debug messages to print the clock values appropriately. Signed-off-by: Tushar Behera --- Changes for v2: * Clocks for EXYNOS4X12 has also been modified. * Debug messages are updated to reflect the change in clock alias. * Updated commit message to better describe the changes. drivers/clk/samsung/clk-exynos4.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index addc738..1bdb882 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -356,8 +356,8 @@ struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { /* list of mux clocks supported in all exynos4 soc's */ struct samsung_mux_clock exynos4_mux_clks[] __initdata = { - MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0), + MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0, "mout_apll"), MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), @@ -385,9 +385,9 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), + MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), MUX_A(mout_core, "mout_core", mout_core_p4210, - SRC_CPU, 16, 1, "mout_core"), + SRC_CPU, 16, 1, "moutcore"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -424,8 +424,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { /* list of mux clocks supported in exynos4x12 soc */ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { - MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, - SRC_CPU, 24, 1), + MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, + SRC_CPU, 24, 1, "mout_mpll"), MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, @@ -449,7 +449,8 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { SRC_DMC, 12, 1, "sclk_mpll"), MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), + MUX_A(mout_core, "mout_core", mout_core_p4x12, + SRC_CPU, 16, 1, "moutcore"), MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), @@ -537,7 +538,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), + DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), DIV_A(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, @@ -1070,9 +1071,9 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", - _get_rate("sclk_apll"), _get_rate("sclk_mpll"), + _get_rate("sclk_apll"), _get_rate("mout_mpll"), _get_rate("sclk_epll"), _get_rate("sclk_vpll"), - _get_rate("arm_clk")); + _get_rate("armclk")); }