From patchwork Thu Jun 6 11:22:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 17592 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f72.google.com (mail-yh0-f72.google.com [209.85.213.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8F67925DEA for ; Thu, 6 Jun 2013 11:36:57 +0000 (UTC) Received: by mail-yh0-f72.google.com with SMTP id f11sf208898yha.3 for ; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=7kfvxHlz3of2T72Mwq6wrnN9VwqprgeWcr8ja+YCC3o=; b=ZytbC2P5zr4Fy6AwslybENmHySM7zM6dy8GD2pN1XFKhN0T8nXsKV7LJc1b5u/jKEb vULjlXsPf8ISP1H/B+Vy6rX88gE1WA+apotXJxVwr34hz+/oML40crO7oH6H1p0PCfEl NrUfZpZrfCRTQtMNLJJKYyF5JA6qrwEy78koQuHPJivyeM3qFVb2+ANzPSd4S5SHIv0Q 1Ys3Wk0z/dCsaIHsyS7/Sdhr8kvcze4WgoDdikdSJc8Rn08h9GsTqM5ZKUjIVSxUbqyR xJciXDwwr6Ufxbi8nhMUPf5nf8ju9SEfju48YF6rCCvzrLwu17EYN1SbffCQbBrm4NMV MSiA== X-Received: by 10.224.165.143 with SMTP id i15mr21095307qay.0.1370518617286; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.128.104 with SMTP id nn8ls1265755qeb.38.gmail; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) X-Received: by 10.220.1.9 with SMTP id 9mr4769381vcd.37.1370518617093; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id ia10si6711764vdb.51.2013.06.06.04.36.57 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:36:57 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id hz10so1876499vcb.38 for ; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) X-Received: by 10.52.170.148 with SMTP id am20mr18660204vdc.75.1370518617002; Thu, 06 Jun 2013 04:36:57 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.10.206 with SMTP id pb14csp63086vcb; Thu, 6 Jun 2013 04:36:56 -0700 (PDT) X-Received: by 10.66.157.229 with SMTP id wp5mr39392843pab.14.1370518615886; Thu, 06 Jun 2013 04:36:55 -0700 (PDT) Received: from mail-pd0-f181.google.com (mail-pd0-f181.google.com [209.85.192.181]) by mx.google.com with ESMTPS id wn4si47509103pbc.205.2013.06.06.04.36.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:36:55 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.181 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=209.85.192.181; Received: by mail-pd0-f181.google.com with SMTP id 14so592441pdj.40 for ; Thu, 06 Jun 2013 04:36:55 -0700 (PDT) X-Received: by 10.66.122.68 with SMTP id lq4mr38099017pab.78.1370518615455; Thu, 06 Jun 2013 04:36:55 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id dr6sm77362405pac.11.2013.06.06.04.36.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:36:54 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH 2/2] clk: exynos4: Add alias for cpufreq related clocks Date: Thu, 6 Jun 2013 16:52:28 +0530 Message-Id: <1370517749-29892-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370517749-29892-1-git-send-email-tushar.behera@linaro.org> References: <1370517749-29892-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQmxwIzG+I7moSa7MCIdxaP0/e+2W3zbDfdKmfn7dR0U1bJC00FIaqiISRN7D2VAcUOsEDta X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. 'armclk', 'moutcore', 'mout_mpll' and 'mout_apll' clock aliases are defined. Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos4.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3c1f888..1e4258a 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -356,8 +356,8 @@ struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { /* list of mux clocks supported in all exynos4 soc's */ struct samsung_mux_clock exynos4_mux_clks[] __initdata = { - MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0), + MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0, "mout_apll"), MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), @@ -385,9 +385,9 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), + MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), MUX_A(mout_core, "mout_core", mout_core_p4210, - SRC_CPU, 16, 1, "mout_core"), + SRC_CPU, 16, 1, "moutcore"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -534,7 +534,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), + DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), DIV_A(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,