From patchwork Tue May 8 09:45:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 8450 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CCB0B23E20 for ; Tue, 8 May 2012 09:45:50 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 83A5FA18370 for ; Tue, 8 May 2012 09:45:50 +0000 (UTC) Received: by yenq6 with SMTP id q6so173733yen.11 for ; Tue, 08 May 2012 02:45:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=iUVUko72nUv8yd76tqbsxqI/J3e6ndKHQbWwKRLV1IE=; b=DgmWmqFaXPUCIM9uZZRIYNyn/MU5IDfyjvGvK/nRVXmDl1bFSWeyY3uO3JN5NUdHzb bju7XZa72ker4oPNCfDh7a5d9O/9NEEcpamQ/3V6Fft1WpHvBrmvl2LUY+3GKJe1X04m 5l+OnMrxdUAc1mL9Y3dSHVmhwUl/H8oKwdVrj7JEH4SY5ts7C12kTvF8UV1jm/8vnwpC GAiB8CyVTExACMc/C14Xn4szd9ah+WX3rvVNhB8q4Qa0b5E34Lh20H1sGBBQdNbw73Et WFuhjMQbZrOkpgtyaMwXT3nSUHwmzzGl57gH7f9QtUaXeVnnW8DOHT9Z1SIyf66/kaL+ rCpw== Received: by 10.50.47.131 with SMTP id d3mr10338880ign.33.1336470349854; Tue, 08 May 2012 02:45:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.73.147 with SMTP id q19csp187528ibj; Tue, 8 May 2012 02:45:49 -0700 (PDT) Received: by 10.14.185.142 with SMTP id u14mr726406eem.41.1336470348566; Tue, 08 May 2012 02:45:48 -0700 (PDT) Received: from eu1sys200aog108.obsmtp.com (eu1sys200aog108.obsmtp.com. [207.126.144.125]) by mx.google.com with SMTP id s5si5764824ees.205.2012.05.08.02.45.39 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 08 May 2012 02:45:48 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.125 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.125; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.125 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob108.postini.com ([207.126.147.11]) with SMTP ID DSNKT6jrQVGtI6+7OIXPoPuEHb/E2c61R0oS@postini.com; Tue, 08 May 2012 09:45:48 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 0D92D3F; Tue, 8 May 2012 09:45:19 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id ADC7A61; Tue, 8 May 2012 07:24:36 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 994F924C2E7; Tue, 8 May 2012 11:45:29 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 8 May 2012 11:45:34 +0200 From: Linus Walleij To: , Cc: Stephen Warren , Shawn Guo , Thomas Abraham , Dong Aisheng , Rajendra Nayak , Haojian Zhuang , Linus Walleij Subject: [PATCH 10/12] ARM: ux500: switch to using pinctrl for uart0 Date: Tue, 8 May 2012 11:45:32 +0200 Message-ID: <1336470332-23816-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.9.2 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlTue/6ZXudN0AUNICeRIF7zch3Y0DMNfYyHydCbHpblcI8ubrgNA4u1IrqDzabVf2C0Dle From: Linus Walleij UART0 had a hack that enabled its pins on init and put it to sleep on the exit callback. Replace this with the pinctrl calls to do the same thing and update the runtime table with the two apropriate states for runtime/active and idle. Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 19 ++++++++++ arch/arm/mach-ux500/board-mop500.c | 62 ++++++++++++++++++++----------- 2 files changed, 60 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 157af7e..dccd29d 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -45,6 +45,10 @@ BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); +/* Sleep modes */ +BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); +BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); +BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -58,6 +62,10 @@ BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); #define DB8500_PIN(pin,conf,dev) \ PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf) +#define DB8500_PIN_SLEEP(pin,conf,dev) \ + PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ + pin, conf) + /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* @@ -115,6 +123,17 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * converted to the pinctrl model. Here we model them as "default" * states. */ + /* Mux in UART0 after initialization */ + DB8500_MUX("u0_a_1", "u0", "uart0"), + DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */ + DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */ + DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ + DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ + /* Sleep state for UART0 */ + DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"), + DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"), + DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"), + DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"), /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index e5c0e6e..1dc3165 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -30,18 +30,17 @@ #include #include #include - #include #include - #include +#include + #include #include #include #include #include -#include #include #include @@ -49,7 +48,6 @@ #include #include -#include "pins-db8500.h" #include "ste-dma40-db8500.h" #include "devices-db8500.h" #include "board-mop500.h" @@ -522,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { }; #endif - -static pin_cfg_t mop500_pins_uart0[] = { - GPIO0_U0_CTSn | PIN_INPUT_PULLUP, - GPIO1_U0_RTSn | PIN_OUTPUT_HIGH, - GPIO2_U0_RXD | PIN_INPUT_PULLUP, - GPIO3_U0_TXD | PIN_OUTPUT_HIGH, -}; - #define PRCC_K_SOFTRST_SET 0x18 #define PRCC_K_SOFTRST_CLEAR 0x1C static void ux500_uart0_reset(void) @@ -550,24 +540,33 @@ static void ux500_uart0_reset(void) udelay(1); } +/* This needs to be referenced by callbacks */ +struct pinctrl *u0_p; +struct pinctrl_state *u0_def; +struct pinctrl_state *u0_sleep; + static void ux500_uart0_init(void) { int ret; - ret = nmk_config_pins(mop500_pins_uart0, - ARRAY_SIZE(mop500_pins_uart0)); - if (ret < 0) - pr_err("pl011: uart pins_enable failed\n"); + if (IS_ERR(u0_p) || IS_ERR(u0_def)) + return; + + ret = pinctrl_select_state(u0_p, u0_def); + if (ret) + pr_err("could not set UART0 defstate\n"); } static void ux500_uart0_exit(void) { int ret; - ret = nmk_config_pins_sleep(mop500_pins_uart0, - ARRAY_SIZE(mop500_pins_uart0)); - if (ret < 0) - pr_err("pl011: uart pins_disable failed\n"); + if (IS_ERR(u0_p) || IS_ERR(u0_sleep)) + return; + + ret = pinctrl_select_state(u0_p, u0_sleep); + if (ret) + pr_err("could not set UART0 idlestate\n"); } static struct amba_pl011_data uart0_plat = { @@ -599,7 +598,28 @@ static struct amba_pl011_data uart2_plat = { static void __init mop500_uart_init(struct device *parent) { - db8500_add_uart0(parent, &uart0_plat); + struct amba_device *uart0_device; + + uart0_device = db8500_add_uart0(parent, &uart0_plat); + if (uart0_device) { + u0_p = pinctrl_get(&uart0_device->dev); + if (IS_ERR(u0_p)) + dev_err(&uart0_device->dev, + "could not get UART0 pinctrl\n"); + else { + u0_def = pinctrl_lookup_state(u0_p, + PINCTRL_STATE_DEFAULT); + if (IS_ERR(u0_def)) { + dev_err(&uart0_device->dev, + "could not get UART0 defstate\n"); + } + u0_sleep = pinctrl_lookup_state(u0_p, + PINCTRL_STATE_SLEEP); + if (IS_ERR(u0_sleep)) + dev_err(&uart0_device->dev, + "could not get UART0 idlestate\n"); + } + } db8500_add_uart1(parent, &uart1_plat); db8500_add_uart2(parent, &uart2_plat); }