From patchwork Tue Mar 6 22:05:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 7124 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5E5B223E74 for ; Tue, 6 Mar 2012 22:29:39 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id F1088A183AE for ; Tue, 6 Mar 2012 22:29:38 +0000 (UTC) Received: by iage36 with SMTP id e36so10317774iag.11 for ; Tue, 06 Mar 2012 14:29:38 -0800 (PST) Received: from mr.google.com ([10.50.195.234]) by 10.50.195.234 with SMTP id ih10mr12090918igc.50.1331072978503 (num_hops = 1); Tue, 06 Mar 2012 14:29:38 -0800 (PST) Received: by 10.50.195.234 with SMTP id ih10mr10047521igc.50.1331072978410; Tue, 06 Mar 2012 14:29:38 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp1310ibg; Tue, 6 Mar 2012 14:29:37 -0800 (PST) Received: by 10.14.47.137 with SMTP id t9mr8648976eeb.5.1331072976513; Tue, 06 Mar 2012 14:29:36 -0800 (PST) Received: from eu1sys200aog102.obsmtp.com (eu1sys200aog102.obsmtp.com. [207.126.144.113]) by mx.google.com with SMTP id q48si17447581eef.182.2012.03.06.14.29.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 06 Mar 2012 14:29:36 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.113; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKT1aPwLadRIxDSgt4gXa/SwmuLkGkhW9A@postini.com; Tue, 06 Mar 2012 22:29:36 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 8BF2871; Tue, 6 Mar 2012 22:05:17 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 2CCB94A; Tue, 6 Mar 2012 20:32:55 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 1FE9FA8065; Tue, 6 Mar 2012 23:05:20 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 6 Mar 2012 23:05:28 +0100 From: Linus Walleij To: , Cc: Stephen Warren , Shawn Guo , Thomas Abraham , Dong Aisheng , Rajendra Nayak , Haojian Zhuang , Linus Walleij Subject: [PATCH 2/4] pinctrl/coh901: use generic pinconf enums and parameters Date: Tue, 6 Mar 2012 23:05:25 +0100 Message-ID: <1331071525-24699-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.8 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQm93HZ4+kTKoWr6heRQbdnkEudEXEsdDyP93csKjnnlZ0OsEaoHYI5e8vwfSfUyz5HVGquH From: Linus Walleij Adjust the COH 901 driver to use the standard enums for biasing and driving pins, alter signature of config function to suit the framework. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-coh901.c | 56 +++++++++----------------------------- 1 files changed, 13 insertions(+), 43 deletions(-) diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index b90c011..724234c 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -26,36 +26,6 @@ #include /* - * Bias modes for U300 GPIOs - * - * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us - * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state - * is not controlled by software - * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high - * impedance to VDD) - */ -#define GPIO_U300_CONFIG_BIAS_UNKNOWN 0x1000 -#define GPIO_U300_CONFIG_BIAS_FLOAT 0x1001 -#define GPIO_U300_CONFIG_BIAS_PULL_UP 0x1002 - -/* - * Drive modes for U300 GPIOs (output) - * - * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and - * low, this is the most typical case and is typically achieved with two - * active transistors on the output - * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain - * (open collector) which means it is usually wired with other output - * ports which are then pulled up with an external resistor - * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain - * (open emitter) which is the same as open drain mutatis mutandis but - * pulled to ground - */ -#define GPIO_U300_CONFIG_DRIVE_PUSH_PULL 0x2000 -#define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN 0x2001 -#define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE 0x2002 - -/* * Register definitions for COH 901 335 variant */ #define U300_335_PORT_STRIDE (0x1C) @@ -181,12 +151,12 @@ struct u300_gpio_confdata { #define BS365_GPIO_NUM_PORTS 5 #define U300_FLOATING_INPUT { \ - .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \ + .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ .output = false, \ } #define U300_PULL_UP_INPUT { \ - .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \ + .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ .output = false, \ } @@ -449,7 +419,7 @@ static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) } static int u300_gpio_config(struct gpio_chip *chip, unsigned offset, - u16 param, unsigned long *data) + enum pin_config_param param, unsigned long data) { struct u300_gpio *gpio = to_u300_gpio(chip); unsigned long flags; @@ -457,16 +427,16 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset, local_irq_save(flags); switch (param) { - case GPIO_U300_CONFIG_BIAS_UNKNOWN: - case GPIO_U300_CONFIG_BIAS_FLOAT: + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: val = readl(U300_PIN_REG(offset, per)); writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); break; - case GPIO_U300_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_UP: val = readl(U300_PIN_REG(offset, per)); writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); break; - case GPIO_U300_CONFIG_DRIVE_PUSH_PULL: + case PIN_CONFIG_DRIVE_PUSH_PULL: val = readl(U300_PIN_REG(offset, pcr)); val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); @@ -474,7 +444,7 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset, << ((offset & 0x07) << 1)); writel(val, U300_PIN_REG(offset, pcr)); break; - case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: val = readl(U300_PIN_REG(offset, pcr)); val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); @@ -482,7 +452,7 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset, << ((offset & 0x07) << 1)); writel(val, U300_PIN_REG(offset, pcr)); break; - case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: + case PIN_CONFIG_DRIVE_OPEN_SOURCE: val = readl(U300_PIN_REG(offset, pcr)); val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); @@ -651,12 +621,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio, /* Deactivate bias mode for output */ u300_gpio_config(&gpio->chip, offset, - GPIO_U300_CONFIG_BIAS_FLOAT, - NULL); + PIN_CONFIG_BIAS_HIGH_IMPEDANCE, + 0); /* Set drive mode for output */ u300_gpio_config(&gpio->chip, offset, - GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL); + PIN_CONFIG_DRIVE_PUSH_PULL, 0); dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", offset, conf->outval); @@ -667,7 +637,7 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio, u300_gpio_set(&gpio->chip, offset, 0); /* Set bias mode for input */ - u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL); + u300_gpio_config(&gpio->chip, offset, conf->bias_mode, 0); dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", offset, conf->bias_mode);