From patchwork Thu Feb 2 04:57:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinayak Holikatti X-Patchwork-Id: 6567 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7DE9423E16 for ; Thu, 2 Feb 2012 04:58:22 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3F150A1853A for ; Thu, 2 Feb 2012 04:58:22 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id z7so3595619iab.11 for ; Wed, 01 Feb 2012 20:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :dkim-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; 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Authentication-Results: mx.google.com; spf=pass (google.com: domain of vinholikatti@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=vinholikatti@gmail.com; dkim=pass header.i=@gmail.com Received: by mail-iy0-f178.google.com with SMTP id k3so3406599iae.37 for ; Wed, 01 Feb 2012 20:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=WynL/uYgVKWU9Yr8CEA2wIs3MRCj15jIgvHE2FYpl6g=; b=Q47ircq4ZTe3RAj4o1xxlbuF2LpIE720gCKjkrXaS3Q9vO9cM5HvKB9W3q9ScB+ZwI ha7iO/C8/bvX8/MEXG7pffY7leDi9q5sjIvSaPJUmUy91RHhQkz2nJSa/cavvSZSFKMk bn6oGvlDfmtARAMgXHz5igji1lH/IdWNIaBuo= Received: by 10.50.170.73 with SMTP id ak9mr1625848igc.3.1328158700730; Wed, 01 Feb 2012 20:58:20 -0800 (PST) Received: from girishks ([115.113.119.130]) by mx.google.com with ESMTPS id ut1sm2141504igc.2.2012.02.01.20.58.14 (version=SSLv3 cipher=OTHER); Wed, 01 Feb 2012 20:58:20 -0800 (PST) From: Vinayak Holikatti To: James.Bottomley@HansenPartnership.com Cc: linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, patches@linaro.org, linux-samsung-soc@vger.kernel.org, saugata.das@linaro.org, arnd@arndb.de, venkat@linaro.org, girish.shivananjappa@linaro.org, vishak.g@samsung.com, k.rajesh@samsung.com, yejin.moon@samsung.com, Santosh Yaraganavi , Vinayak Holikatti Subject: [PATCH 3/4] [SCSI] ufshcd: UFSHCI error handling Date: Thu, 2 Feb 2012 10:27:28 +0530 Message-Id: <1328158649-4137-4-git-send-email-vinholikatti@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1328158649-4137-1-git-send-email-vinholikatti@gmail.com> References: <1328158649-4137-1-git-send-email-vinholikatti@gmail.com> From: Santosh Yaraganavi UFSHCI error handling includes support for: - UFS host controller errors - System bus errors - Unipro errors Signed-off-by: Santosh Yaraganavi Signed-off-by: Vinayak Holikatti Reviewed-by: Arnd Bergmann Reviewed-by: Saugata Das Reviewed-by: Vishak G Reviewed-by: Girish K S --- drivers/scsi/ufs/ufshcd.c | 104 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 104 insertions(+), 0 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 23d758b..1bfae84 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -64,6 +64,7 @@ #include #include #include +#include #include "ufs.h" #include "ufshci.h" @@ -153,9 +154,13 @@ struct uic_command { * @nutrs: Transfer Request Queue depth supported by controller * @nutmrs: Task Management Queue depth supported by controller * @active_uic_cmd: handle of active UIC command + * @ufshcd_tm_wait_queue: wait queue for task management + * @tm_condition: array of condition varibles for task management * @ufshcd_state: UFSHCD states * @int_enable_mask: Interrupt Mask Bits * @uic_workq: Work queue for UIC completion handling + * @feh_workq: Work queue for fatal controller error handling + * @errors: HBA errors */ struct ufs_hba { void __iomem *mmio_base; @@ -201,6 +206,10 @@ struct ufs_hba { /* Work Queues */ struct work_struct uic_workq; + struct work_struct feh_workq; + + /* HBA Errors */ + u32 errors; }; /** @@ -924,6 +933,9 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba) /* Configure interrupt aggregation */ ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG); + if (UFSHCD_STATE_RESET == hba->ufshcd_state) + scsi_unblock_requests(hba->host); + hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; scsi_scan_host(hba->host); @@ -1009,6 +1021,53 @@ static int ufshcd_initialize_hba(struct ufs_hba *hba) } /** + * ufshcd_do_reset - reset the host controller + * @hba: per adapter instance + * + * Returns 0 on success, non-zero value on failure + */ +static int ufshcd_do_reset(struct ufs_hba *hba) +{ + struct ufshcd_lrb *lrbp; + unsigned long flags; + int tag; + + /* block commands from midlayer */ + scsi_block_requests(hba->host); + + spin_lock_irqsave(hba->host->host_lock, flags); + hba->ufshcd_state = UFSHCD_STATE_RESET; + + /* send controller to reset state */ + writel(0, (UFSHCD_MMIO_BASE + REG_CONTROLLER_ENABLE)); + + /* abort outstanding commands */ + for (tag = 0; tag < hba->host->can_queue; tag++) { + lrbp = &hba->lrb[tag]; + + /* if lrbp->cmd is not NULL, the command is outstanding */ + if (lrbp->cmd) { + scsi_dma_unmap(lrbp->cmd); + lrbp->cmd->result = DID_RESET << 16; + lrbp->cmd->scsi_done(lrbp->cmd); + lrbp->cmd = NULL; + } + } + + /* disable all the interrupts */ + ufshcd_int_config(hba, UFSHCD_INT_DISABLE); + spin_unlock_irqrestore(hba->host->host_lock, flags); + + /* start the initialization process */ + if (ufshcd_initialize_hba(hba)) { + dev_err(&hba->pdev->dev, + "Reset: Controller initialization failed\n"); + return -EINVAL; + } + return 0; +} + +/** * ufshcd_slave_alloc - handle initial scsi devie configurations * @sdev: pointer to scsi device * @@ -1215,12 +1274,56 @@ static void ufshcd_uic_cc_handler (struct work_struct *work) } /** + * ufshcd_fatal_err_handler - handle fatal errors + * @hba: per adapter instance + */ +static void ufshcd_fatal_err_handler(struct work_struct *work) +{ + struct ufs_hba *hba; + hba = container_of(work, struct ufs_hba, feh_workq); + + /* check if reset is already in progress */ + if (UFSHCD_STATE_RESET != hba->ufshcd_state) + ufshcd_do_reset(hba); +} + +/** + * ufshcd_err_handler - Check for fatal errors + * @work: pointer to a work queue structure + */ +static void ufshcd_err_handler(struct ufs_hba *hba) +{ + u32 reg; + + if (hba->errors & INT_FATAL_ERRORS) + goto fatal_eh; + + if (hba->errors & UIC_ERROR) { + + reg = readl(UFSHCD_MMIO_BASE + + REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); + if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) + goto fatal_eh; + } + + return; + +fatal_eh: + hba->ufshcd_state = UFSHCD_STATE_ERROR; + schedule_work(&hba->feh_workq); +} + +/** * ufshcd_sl_intr - Interrupt service routine * @hba: per adapter instance * @intr_status: contains interrupts generated by the controller */ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) { + hba->errors = UFSHCD_ERROR_MASK & intr_status; + if (hba->errors) + ufshcd_err_handler(hba); + if (intr_status & UIC_COMMAND_COMPL) schedule_work(&hba->uic_workq); @@ -1446,6 +1549,7 @@ ufshcd_probe(struct pci_dev *pdev, const struct pci_device_id *id) /* Initialize work queues */ INIT_WORK(&hba->uic_workq, ufshcd_uic_cc_handler); + INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler); /* IRQ registration */ err = request_irq(pdev->irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);