From patchwork Fri Jan 13 15:20:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 6187 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EE9F523F83 for ; Fri, 13 Jan 2012 15:20:16 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id E1FE9A1803A for ; Fri, 13 Jan 2012 15:20:16 +0000 (UTC) Received: by eaae12 with SMTP id e12so213353eaa.11 for ; Fri, 13 Jan 2012 07:20:16 -0800 (PST) Received: by 10.204.41.143 with SMTP id o15mr639881bke.63.1326468016680; Fri, 13 Jan 2012 07:20:16 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs32139bkc; Fri, 13 Jan 2012 07:20:16 -0800 (PST) Received: by 10.213.19.143 with SMTP id a15mr387960ebb.32.1326468015133; Fri, 13 Jan 2012 07:20:15 -0800 (PST) Received: from eu1sys200aog102.obsmtp.com (eu1sys200aog102.obsmtp.com. [207.126.144.113]) by mx.google.com with SMTP id p55si5966468eeh.147.2012.01.13.07.20.10 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 13 Jan 2012 07:20:15 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.113; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKTxBLqoD4UAbjIOLEmod+Cgh+/KMA537g@postini.com; Fri, 13 Jan 2012 15:20:14 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BB5D1D1; Fri, 13 Jan 2012 15:11:40 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1E61C87A; Fri, 13 Jan 2012 15:20:07 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id C84B724C075; Fri, 13 Jan 2012 16:19:58 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Fri, 13 Jan 2012 16:20:06 +0100 From: Linus Walleij To: Samuel Ortiz , Cc: Mattias Nilsson , Bengt Jonsson , Daniel Willerud , Linus Walleij Subject: [PATCH 1/8] mfd/db8500-prcmu: remove U8400 legacy Date: Fri, 13 Jan 2012 16:20:03 +0100 Message-ID: <1326468003-11683-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.8 MIME-Version: 1.0 From: Daniel Willerud This removes the U8400 legacy from PRCMU and cpufreq drivers. This platform has no current in-kernel users. Signed-off-by: Daniel Willerud Signed-off-by: Linus Walleij --- drivers/cpufreq/db8500-cpufreq.c | 13 +++++-------- drivers/mfd/db8500-prcmu.c | 26 ++------------------------ include/linux/mfd/db8500-prcmu.h | 6 ------ 3 files changed, 7 insertions(+), 38 deletions(-) diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c index f500201..a22ffa5 100644 --- a/drivers/cpufreq/db8500-cpufreq.c +++ b/drivers/cpufreq/db8500-cpufreq.c @@ -22,11 +22,11 @@ static struct cpufreq_frequency_table freq_table[] = { }, [1] = { .index = 1, - .frequency = 300000, + .frequency = 400000, }, [2] = { .index = 2, - .frequency = 600000, + .frequency = 800000, }, [3] = { /* Used for MAX_OPP, if available */ @@ -113,12 +113,9 @@ static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy) BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table)); - if (!prcmu_is_u8400()) { - freq_table[1].frequency = 400000; - freq_table[2].frequency = 800000; - if (prcmu_has_arm_maxopp()) - freq_table[3].frequency = 1000000; - } + if (prcmu_has_arm_maxopp()) + freq_table[3].frequency = 1000000; + pr_info("db8500-cpufreq : Available frequencies:\n"); for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) pr_info(" %d Mhz\n", freq_table[i].frequency/1000); diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index af8e0ef..b911963 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -503,9 +503,6 @@ static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { /* PLLDIV=12, PLLSW=4 (PLLDDR) */ #define PRCMU_DSI_CLOCK_SETTING 0x0000008C -/* PLLDIV=8, PLLSW=4 (PLLDDR) */ -#define PRCMU_DSI_CLOCK_SETTING_U8400 0x00000088 - /* DPI 50000000 Hz */ #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ (16 << PRCMU_CLK_PLL_DIV_SHIFT)) @@ -514,9 +511,6 @@ static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { /* D=101, N=1, R=4, SELDIV2=0 */ #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 -/* D=70, N=1, R=3, SELDIV2=0 */ -#define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146 - #define PRCMU_ENABLE_PLLDSI 0x00000001 #define PRCMU_DISABLE_PLLDSI 0x00000000 #define PRCMU_RELEASE_RESET_DSS 0x0000400C @@ -539,19 +533,14 @@ static struct { int db8500_prcmu_enable_dsipll(void) { int i; - unsigned int plldsifreq; /* Clear DSIPLL_RESETN */ writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); /* Unclamp DSIPLL in/out */ writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); - if (prcmu_is_u8400()) - plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400; - else - plldsifreq = PRCMU_PLLDSI_FREQ_SETTING; /* Set DSI PLL FREQ */ - writel(plldsifreq, PRCM_PLLDSI_FREQ); + writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); /* Enable Escape clocks */ writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); @@ -583,12 +572,6 @@ int db8500_prcmu_disable_dsipll(void) int db8500_prcmu_set_display_clocks(void) { unsigned long flags; - unsigned int dsiclk; - - if (prcmu_is_u8400()) - dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400; - else - dsiclk = PRCMU_DSI_CLOCK_SETTING; spin_lock_irqsave(&clk_mgt_lock, flags); @@ -596,7 +579,7 @@ int db8500_prcmu_set_display_clocks(void) while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) cpu_relax(); - writel(dsiclk, PRCM_HDMICLK_MGT); + writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); @@ -642,11 +625,6 @@ bool prcmu_has_arm_maxopp(void) PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; } -bool prcmu_is_u8400(void) -{ - return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0; -} - /** * prcmu_get_boot_status - PRCMU boot status checking * Returns: the current PRCMU boot status diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 60d27f7..0dc9017 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -500,7 +500,6 @@ int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); bool prcmu_has_arm_maxopp(void); -bool prcmu_is_u8400(void); int prcmu_set_ape_opp(u8 opp); int prcmu_get_ape_opp(void); int prcmu_request_ape_opp_100_voltage(bool enable); @@ -574,11 +573,6 @@ static inline bool prcmu_has_arm_maxopp(void) return false; } -static inline bool prcmu_is_u8400(void) -{ - return false; -} - static inline int prcmu_set_ape_opp(u8 opp) { return 0;