From patchwork Wed Jul 6 16:37:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2487 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8D9D02413B for ; Wed, 6 Jul 2011 16:31:32 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 5CD19A18AC1 for ; Wed, 6 Jul 2011 16:31:32 +0000 (UTC) Received: by mail-qw0-f52.google.com with SMTP id 8so52782qwb.11 for ; Wed, 06 Jul 2011 09:31:32 -0700 (PDT) Received: by 10.229.62.194 with SMTP id y2mr6738277qch.4.1309969892137; Wed, 06 Jul 2011 09:31:32 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs83896qcf; Wed, 6 Jul 2011 09:31:31 -0700 (PDT) Received: by 10.42.244.195 with SMTP id lr3mr4293052icb.90.1309969891542; Wed, 06 Jul 2011 09:31:31 -0700 (PDT) Received: from VA3EHSOBE002.bigfish.com (va3ehsobe002.messaging.microsoft.com [216.32.180.12]) by mx.google.com with ESMTPS id k6si4221819icv.91.2011.07.06.09.31.31 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jul 2011 09:31:31 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.180.12 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=216.32.180.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.12 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: from mail171-va3-R.bigfish.com (10.7.14.247) by VA3EHSOBE002.bigfish.com (10.7.40.22) with Microsoft SMTP Server id 14.1.225.22; Wed, 6 Jul 2011 16:31:30 +0000 Received: from mail171-va3 (localhost.localdomain [127.0.0.1]) by mail171-va3-R.bigfish.com (Postfix) with ESMTP id 80589B100CF; Wed, 6 Jul 2011 16:31:30 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail171-va3 (localhost.localdomain [127.0.0.1]) by mail171-va3 (MessageSwitch) id 1309969888850926_5897; Wed, 6 Jul 2011 16:31:28 +0000 (UTC) Received: from VA3EHSMHS016.bigfish.com (unknown [10.7.14.240]) by mail171-va3.bigfish.com (Postfix) with ESMTP id 9968C568052; Wed, 6 Jul 2011 16:31:28 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS016.bigfish.com (10.7.99.26) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 6 Jul 2011 16:31:22 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Wed, 6 Jul 2011 11:31:21 -0500 Received: from S2100-06.ap.freescale.net (S2100-06.ap.freescale.net [10.192.242.125]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p66GVE5q016803; Wed, 6 Jul 2011 11:31:19 -0500 (CDT) From: Shawn Guo To: CC: , , , Shawn Guo , Sascha Hauer , Grant Likely Subject: [PATCH v3 2/3] ARM: mxc: use ARCH_NR_GPIOS to define gpio number Date: Thu, 7 Jul 2011 00:37:42 +0800 Message-ID: <1309970263-13239-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1309970263-13239-1-git-send-email-shawn.guo@linaro.org> References: <1309970263-13239-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com The patch removes MXC_GPIO_IRQS and instead uses ARCH_NR_GPIOS to define gpio number. This change is need when we change mxc gpio driver to be device tree aware. When migrating the driver to device tree, pdev->id becomes unusable. It requires driver get gpio range from gpio core, which will dynamically allocates number from ARCH_NR_GPIOS to 0. As a bonus point, it removes lines of '#if' and make the code a little bit cleaner. The side effect is the waste of number. But this is not a point when we go single image. Signed-off-by: Shawn Guo Cc: Sascha Hauer Cc: Grant Likely --- arch/arm/plat-mxc/include/mach/irqs.h | 21 +++------------------ 1 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 35c89bc..00e812b 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ +#include + /* * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ @@ -22,30 +24,13 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -/* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_SOC_IMX53 -#define MXC_GPIO_IRQS (32 * 7) -#elif defined CONFIG_ARCH_MX2 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_SOC_IMX50 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX25 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_SOC_IMX51 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use * these. If you need more, increase MXC_BOARD_IRQS, but keep it * within sensible limits. */ -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #define MXC_BOARD_IRQS 80