From patchwork Wed Dec 11 12:46:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181202 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp481271ile; Wed, 11 Dec 2019 04:45:26 -0800 (PST) X-Google-Smtp-Source: APXvYqxFSFNZJ5B0BifLeHTKopfmBFz7v5nKpC/EcnlZJRnhqrgeIQX1KTwgNlmYkHQCnp0c8cYh X-Received: by 2002:aca:33d5:: with SMTP id z204mr2471217oiz.120.1576068326692; Wed, 11 Dec 2019 04:45:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576068326; cv=none; d=google.com; s=arc-20160816; b=f92No5l0FI0hFPKJT9g1GZb197eZQzH+g5PeROdD9n+JB2p6je5JFtjyIqfrmJtrtY XmxRwaJn4q7XVd1YWbLcRfp9plAIlFtl+G9lYn3SmQMPnz9jwot77oONRXm/Tq3my237 8RiVttnpyDJ6vp8ENMHS5FdkSJFqmzPy9xh2qqm/1q2eZGm2pFqTkYh50PY1wYM/cvDw 9dy0BeXJiE8EJodLMw6qqLh4t/jCDZtJ6i1VPzVu9tXkIlfLgtbiZ03uVbHv33DSU0rR sdNuWn3n1ajt/GR9n33PT3qvxgEqoJc9r3KqLWb6rGSfu5ISDfUjiRZ+HGSk9M/V7j92 7KTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=OE99JeSd1ur9H7sMDQrhfvYhHqNRrzL04S/LysYScMs=; b=qHncr5fjepidcwJftQCQzTCKG+NfhnoPUZQa7S7uEjDgcwXdKKSRzR3ORFsq2tLAAf J8U7zoO1EfUIh7K4YeZBuqTARc+MT+p1Hr2LPX97CQXqQngtGeTpF2KVVRP4ZPWTmRN4 eloIeVsWH1DjWY75wddn+EOCnJr40gc423xS8HU/ru1PztQRQ5sMMJxa9pwfnaMZpVk9 NSI64M4mLfsWMh2ESyn1j1tcQSGKvliBynTaiLiA7qZ/KffSeEKEBIQG7YL3FScotzP9 P2R0IBK1du/lVdXjzKW0rdtw+k71dOVRQY9fRBVExvm0PyvPmcJozsALb57D6j+RWf8m J74w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="s07zZQl/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p22si973548ota.43.2019.12.11.04.45.26; Wed, 11 Dec 2019 04:45:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="s07zZQl/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729374AbfLKMpZ (ORCPT + 27 others); Wed, 11 Dec 2019 07:45:25 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:35786 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727402AbfLKMpU (ORCPT ); Wed, 11 Dec 2019 07:45:20 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBBCiwt2089410; Wed, 11 Dec 2019 06:44:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576068298; bh=OE99JeSd1ur9H7sMDQrhfvYhHqNRrzL04S/LysYScMs=; h=From:To:CC:Subject:Date; b=s07zZQl/I/+upfp1a7uutKA1zM3iv8WSqmOTUtUpQx0CK20B+5bGr46hmHV2ZSnE6 XNLM1KaMG8zFIt31uDaFA65zxpRPZpjQNluH1519lWYkrlhvk8X2+yjO98+9mCwugA asgJA0BPjbwUb6XDcu3Gk7oBnBu0vSpzJ0wyz5BQ= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBBCivUQ108608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 11 Dec 2019 06:44:57 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 11 Dec 2019 06:44:57 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 11 Dec 2019 06:44:57 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBBCirfh125451; Wed, 11 Dec 2019 06:44:54 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Gustavo Pimentel CC: Murali Karicheri , Jingoo Han , Kishon Vijay Abraham I , , , , Xiaowei Bao Subject: [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core Date: Wed, 11 Dec 2019 18:16:04 +0530 Message-ID: <20191211124608.887-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Existing MSI-X support in Endpoint core has limitations: 1) MSIX table (which is mapped to a BAR) is not allocated by anyone. Ideally this should be allocated by endpoint function driver. 2) Endpoint controller can choose any random BARs for MSIX table (irrespective of whether the endpoint function driver has allocated memory for it or not) In order to avoid these limitations, pci_epc_set_msix() is modified to include BAR Indicator register (BIR) configuration and MSIX table offset as arguments. This series also fixed MSIX support in dwc driver and add MSI-X support in Cadence PCIe driver. The previous version of Cadence EP MSI-X support is @ [1]. This series is created on top of [2] [1] -> https://patchwork.ozlabs.org/patch/971160/ [2] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com Alan Douglas (1): PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I (3): PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table address PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt .../pci/controller/cadence/pcie-cadence-ep.c | 112 +++++++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 10 ++ drivers/pci/controller/dwc/pci-keystone.c | 5 +- .../pci/controller/dwc/pcie-designware-ep.c | 61 +++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/endpoint/functions/pci-epf-test.c | 31 ++++- drivers/pci/endpoint/pci-epc-core.c | 7 +- drivers/pci/endpoint/pci-epf-core.c | 2 + include/linux/pci-epc.h | 6 +- include/linux/pci-epf.h | 15 +++ 10 files changed, 207 insertions(+), 43 deletions(-) -- 2.17.1