From patchwork Thu Nov 14 14:59:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 179447 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp11169988ilf; Thu, 14 Nov 2019 07:00:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwnMk7bnXLgvDdZOAu7Xx5iBJDF3XOpbobfvoLU9rSW34rBY2MecJ0ZFkc0RksRibGHpZUu X-Received: by 2002:aa7:cd52:: with SMTP id v18mr1731428edw.280.1573743603629; Thu, 14 Nov 2019 07:00:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573743603; cv=none; d=google.com; s=arc-20160816; b=gB/OPq9HXOiveP0UjJvxTwV9C2zJITugGsxxxGJACSBUPiUgC5dykmgpIVOIvKMWUy e6wkd1JU6hQq+cy/w/SlIqzZGYTRA8esTnw9ftQ0XqxJGF7gHWbK2x2rzKKvdsxHlN1V /vbTrj1fBx/QkRY7/3qkEusUt2UgIEhUUCFmP3R3Fg4ieApPpElYJONJ6UKlwCBlGWvu +1sFDS0Wf4d170Nrp6vnX64h9rITxB3WwlGclPUAittOEPJIGJ6FGikZT+P5bRbTK1h6 ATZLbruvIRKc9U5yvod1WOo/QwWugwkULuNRMtVnRzNQ6BkVNeZe8/LoGwf9m8T7lAqb H9ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=exEwCYrPI6soFjExMSstLtC9oRsVv5U8fIXWXdK7y2M=; b=VmXY+im8KGqRgJN+qKmc5yHHtvFIiWT+ZGaN0JPAcZ61c7jrrwfHCVLLRqBVQKEEHR jn5mbNPLufwmRQEjWaoK3hrCSX7RWwRvMIhWEdUqKL0xQeBQ1ISQyLC7Js6781RqLvKJ hIDh+eqrTkOCBEK5ljN0GkY8mnEeKyrm3cBbdC2TOVs1dg8wpyYuH2iQCbTnN4vhj4zr vAAGmU2e/kx8OTbiaHMdOm6qoni12v18S7/mNQ5TIOP02TasZFVzlOuJ+4Jr3YsHUqLq QQZrpt1gZ8QCPkusee51Y4sgFWHYmW5908nOGm5mPmpKi5hYhDoTvtuiSgMmcf0tKICe 8EvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i14si4010117edr.68.2019.11.14.07.00.03; Thu, 14 Nov 2019 07:00:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726473AbfKNO76 (ORCPT + 26 others); Thu, 14 Nov 2019 09:59:58 -0500 Received: from foss.arm.com ([217.140.110.172]:44606 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726251AbfKNO76 (ORCPT ); Thu, 14 Nov 2019 09:59:58 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFA3A328; Thu, 14 Nov 2019 06:59:57 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B07C33F52E; Thu, 14 Nov 2019 06:59:56 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, james.morse@arm.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, suzuki.poulose@arm.com Subject: [PATCH 0/5] arm64: Add workaround for Cortex-A77 erratum 1542418 Date: Thu, 14 Nov 2019 14:59:13 +0000 Message-Id: <20191114145918.235339-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds workaround for Arm erratum 1542418 which affects Cortex-A77 cores (r0p0 - r1p0). Affected cores may execute stale instructions from the L0 macro-op cache violating the prefetch-speculation-protection guaranteed by the architecture. This happens when the when the branch predictor bases its predictions on a branch at this address on the stale history due to ASID or VMID reuse. The workaround is to invalidate the branch history before reusing any ASID for a new address space. This is done by ensuring 60 ASIDs are selected before any ASID is reused. James Morse (5): arm64: Add MIDR encoding for Arm Cortex-A77 arm64: mm: Workaround Cortex-A77 erratum 1542418 on ASID rollover arm64: Workaround Cortex-A77 erratum 1542418 on boot due to kexec KVM: arm64: Workaround Cortex-A77 erratum 1542418 on VMID rollover KVM: arm/arm64: Don't invoke defacto-CnP on first run Documentation/arm64/silicon-errata.rst | 2 + arch/arm/include/asm/kvm_mmu.h | 5 ++ arch/arm64/Kconfig | 16 ++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/kvm_mmu.h | 15 ++++++ arch/arm64/include/asm/mmu_context.h | 1 + arch/arm64/kernel/cpu_errata.c | 21 ++++++++ arch/arm64/mm/context.c | 73 +++++++++++++++++++++++++- virt/kvm/arm/arm.c | 23 +++++--- 10 files changed, 151 insertions(+), 10 deletions(-) -- 2.23.0