Message ID | 20190405135936.7266-1-will.deacon@arm.com |
---|---|
Headers | show |
Series | Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb()) | expand |
On Fri, Apr 5, 2019 at 3:59 AM Will Deacon <will.deacon@arm.com> wrote: > > I've also pushed this series out here: > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/mmiowb > > and I would like to get it into -next once the first patch has been acked. Ack on it all. With the afore-mentioned slight worry about non-spinlocked IO ordering, but I _think_ it's purely limited to ia64 and wmb() and friends should work elsewhere? Or did I miss something? I think the ia64() mb/rmb/wmb stuff only works on normal memory on ia64. Linus
On Fri, Apr 05, 2019 at 05:55:37AM -1000, Linus Torvalds wrote: > On Fri, Apr 5, 2019 at 3:59 AM Will Deacon <will.deacon@arm.com> wrote: > > > > I've also pushed this series out here: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/mmiowb > > > > and I would like to get it into -next once the first patch has been acked. > > Ack on it all. Thanks. > With the afore-mentioned slight worry about non-spinlocked IO > ordering, but I _think_ it's purely limited to ia64 and wmb() and > friends should work elsewhere? > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > works on normal memory on ia64. I was worried about RISC-V, but actually their wmb() is "fence ow,ow" which I think is stronger than their mmiowb() "fence o,w" implementation. Everybody else should be fine with wmb() afaict, so if a driver writer is smart enough to want this ordering outside of spinlocks, they can do that for everybody apart from ia64. Will
On Fri, Apr 5, 2019 at 6:09 AM Will Deacon <will.deacon@arm.com> wrote: > > > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > > works on normal memory on ia64. > > I was worried about RISC-V, but actually their wmb() is "fence ow,ow" > which I think is stronger than their mmiowb() "fence o,w" implementation. Also with smp_store_release -> smp_load_acquire kind of ordering? Again, this is not at all a NAK - I think we should do this - just perhaps a request to add a note to the commit and make people aware of the issue. I suspect very few drivers use non-locking serialization to begin with. Linus
On Fri, Apr 05, 2019 at 06:15:12AM -1000, Linus Torvalds wrote: > On Fri, Apr 5, 2019 at 6:09 AM Will Deacon <will.deacon@arm.com> wrote: > > > > > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > > > works on normal memory on ia64. > > > > I was worried about RISC-V, but actually their wmb() is "fence ow,ow" > > which I think is stronger than their mmiowb() "fence o,w" implementation. > > Also with smp_store_release -> smp_load_acquire kind of ordering? Hmm, to be honest, I'm not convinced that smp_load_acquire() is ordered wrt subsequent I/O on RISC-V anyway, so in the pattern of: CPU 0: writel(1, dev); wmb(); smp_store_release(&x, 1); CPU 1: if (smp_load_acquire(&x) == 1) writel(2, dev) then I think it's actually the control dependency in CPU 1 that provides the expected ordering. That's probably quite fragile. > Again, this is not at all a NAK - I think we should do this - just > perhaps a request to add a note to the commit and make people aware of > the issue. Right, I'll do that. Will