From patchwork Tue Oct 16 12:49:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 148934 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5045613lji; Tue, 16 Oct 2018 05:51:11 -0700 (PDT) X-Google-Smtp-Source: ACcGV60SzYldNKNsLbsGtz9RB96Ga1sSHWlS+zoVbsIqsI65Ov9uaqkdX631qDDYZhxjCbhvZjty X-Received: by 2002:a63:cc:: with SMTP id 195-v6mr19775185pga.44.1539694270884; Tue, 16 Oct 2018 05:51:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539694270; cv=none; d=google.com; s=arc-20160816; b=gaHicRiB5WdLGqTmodsKUtyrmMKn1vZFRfdXjodwAmTDmdXuCYnjjJVcEH6KLmmKHS zxJDTrzC4mVOYmHIn4uOYUjADv1nWBYYrMfuu3LW/4pOTAhiswMvvGYh7trd2mYMfQrx aW4uvt3hzh4tvSxQVYUaEtWc3E2EyFdk+EFG1ltOk79CeZwmZhhok6Ra9xotbpfGquCW H6yzY5Y9BGD10xhe8C+cRPpnbVNgAx6nUiWwKzG5ODDrFtAKhAe0+mapjplsVSxpRqX+ wqxTYZ0nbFt3m2+0S51N+zvk60zTmxKlg4J5tTLKbWH3si72IFXFMnbmFiCPBvKAfXgp T35g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=cim2jV54EW3+xtdu5n+0jjv+5UZ3N6k2F/+f/S0t40A=; b=CF5vW+JNQNm5vwuHXK0kudjzay4wwsYnW+y62F2CNkwS0SyqIOqiggUgel5Lj3Rh+V jvLqQ/EqC6+QH6vrhLEC30CZyEkPSkoBhFLWC9aKFz6VKW5C8uGYQW9tNvvIr2kDcGmg A92jcZxeVYabO3Mtr7cvY0UsPANEQDtqjYIdt4nn9ITCnq2uMCidIOz4b2ZXYYQcTPaV LPsM+Kniu6IRDGqrwsYR7HzOihVtxscfs0FKRa3hTpKCHhL/Ncsh2WxXmEFIWjTxw2hh l8puQn/mNm2vW7r67+7WYXrfvonPwvWqdhkq9EHF5HJpH00JM60rO9XhoBWaOyNkPkv+ i8Qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h4-v6si14631617plr.343.2018.10.16.05.51.10; Tue, 16 Oct 2018 05:51:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727162AbeJPUl3 (ORCPT + 32 others); Tue, 16 Oct 2018 16:41:29 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:38578 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726986AbeJPUl2 (ORCPT ); Tue, 16 Oct 2018 16:41:28 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 926AC47ACEC5B; Tue, 16 Oct 2018 20:51:04 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.399.0; Tue, 16 Oct 2018 20:50:58 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , , Subject: [PATCH v4 0/4] arm64 SMMUv3 PMU driver with IORT support Date: Tue, 16 Oct 2018 13:49:16 +0100 Message-ID: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a driver for the SMMUv3 PMU into the perf framework. It includes an IORT update to support PM Counter Groups. This is based on the initial work done by Neil Leeder[1] SMMUv3 PMCG devices are named as smmuv3_pmcg_ where is the physical page address of the SMMU PMCG. For example, the PMCG at 0xff88840000 is named smmuv3_pmcg_ff88840 Usage example: For common arch supported events: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1, filter_span=1,filter_stream_id=0x42/ -a netperf For IMP DEF events: perf stat -e smmuv3_pmcg_ff88840/event=id/ -a netperf This is sanity tested on a HiSilicon platform that requires a quirk to run it properly. As per HiSilicon erratum #162001800, PMCG event counter registers (SMMU_PMCG_EVCNTRn) on HiSilicon Hip08 platforms are read only and this prevents the software from setting the initial period on event start. Unfortunately we were a bit late in the cycle to detect this issue and now require software workaround for this. Patch #4 is added to this series to provide a workaround for this issue. Further testing on supported platforms are very much welcome. v3 --> v4 -Addressed comments from Jean and Robin. -Merged dma config callbacks as per Lorenzo's comments(patch #1). -Added handling of Global(Counter0) filter settings mode(patch #2). -Added patch #4 to address HiSilicon erratum #162001800 - v2 --> v3 -Addressed comments from Robin. -Removed iort helper function to retrieve the PMCG reference smmu. -PMCG devices are now named using the base address v1 --> v2 - Addressed comments from Robin. - Added an helper to retrieve the associated smmu dev and named PMUs to make the association visible to user. - Added MSI support for overflow irq [1]https://www.spinics.net/lists/arm-kernel/msg598591.html Neil Leeder (2): acpi: arm64: add iort support for PMCG perf: add arm64 smmuv3 pmu driver Shameer Kolothum (2): perf/smmuv3: Add MSI irq support perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk drivers/acpi/arm64/iort.c | 97 ++++- drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/arm_smmuv3_pmu.c | 959 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1045 insertions(+), 21 deletions(-) create mode 100644 drivers/perf/arm_smmuv3_pmu.c -- 2.7.4