From patchwork Fri Sep 21 10:21:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147189 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp627559ljw; Fri, 21 Sep 2018 03:22:51 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYGSvqV9oFJhowmnhDsRpvCA1ZBLexCEF/j7VD4MKJNCvi+gFUkExO795ZqQTXfYUHQw/hC X-Received: by 2002:a63:5ec5:: with SMTP id s188-v6mr3810053pgb.126.1537525370989; Fri, 21 Sep 2018 03:22:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525370; cv=none; d=google.com; s=arc-20160816; b=ZZqsglJ0cJ5wiVJ7l7zu9Ok37QwWQi5nTSlTwVgENUL9zXQucjNB6O4nW78CRO3pZp YOzI+0PpE0XRC6dXCJnzOny5g7/Bt5QP37oab3nVebb/rJZLbtoCiv0zlYshrIyP6KjB 5sr255N7gh+HN7WDm2QXDWjsjLeiB6/+eOtCJjrR/yBdgQ6E6vD50cSb7k221/rheOTv gK/81MfQIiiRPg6ck7RPJmCqqNrqOukHo1QP1zP0sGW1s2j4nnjA6TMKM9tylRwpuZJ5 u2XXMDhUqRQ2OothjZJUv7SaCPTuD2M1G82HAILz9fjzGfD3xhIXpR8bQKHKBIskA+S3 M6Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=IrJAtwRCt30w4PmzwQJ2ADd8n81WHgGBoHehyP3FbSM=; b=ZSLp8rVe8Snb46trLlDM3ah/5bg548sjeUJO4KWj5TkuojWM00aGThw87eY8XrgjBj ztxTnYofS1bGtlhytmY3VMVKMRKRgFPFI9YSr9Nvodd9HSkmyqrCkVOC8StONpAYhJZf qBigg3h4UDmIK82zkjOYPd/iExL0F6au/biVQJjV0ISFeRXZhEmv9jpLgRQFBg445RN2 VXpCLvHiMB5puCInd61snJCPIypFNXqkUTEq+l1PZUrIafSwL7Mp4v/zXbKlj1NIfWLj hSGjldJ6MEw3Zfs38qa5+pWe3sLPkebbjOoFU/ui1TJ5PULq7zgw3TdTLTC22NewensX Qg9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UJCT09uV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t71-v6si1571830pgd.352.2018.09.21.03.22.50; Fri, 21 Sep 2018 03:22:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UJCT09uV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389603AbeIUQLA (ORCPT + 32 others); Fri, 21 Sep 2018 12:11:00 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34916 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727554AbeIUQLA (ORCPT ); Fri, 21 Sep 2018 12:11:00 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMKMK030282; Fri, 21 Sep 2018 05:22:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525340; bh=IrJAtwRCt30w4PmzwQJ2ADd8n81WHgGBoHehyP3FbSM=; h=From:To:CC:Subject:Date; b=UJCT09uVfEjc+vKlWhMa253gf45caAw6Jmc54gq5rGa/DNk05NQ1pN+WtqzRY7oqN P4ZtSwRXoAu5+vGnOaEh3/pkQLPvrmArb9xtNupLXhxCeQ+Rz0zDfWakk4WTv1auXC 5mdKSIhlNhdmHjkvUFiRD8l6MaJXB7HSGkion4GE= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMKG8028732; Fri, 21 Sep 2018 05:22:20 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:19 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:20 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt4032280; Fri, 21 Sep 2018 05:22:15 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 00/40] Cleanup pci-keystone.c and Add AM654 PCIe Support Date: Fri, 21 Sep 2018 15:51:15 +0530 Message-ID: <20180921102155.22839-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654 uses Synopsys core revision 4.90a and uses the same TI wrapper as used in keystone2 with certain modification. Hence AM654 will use the same pci wrapper driver pci-keystone.c The initial support for AM654 was merged recently [1] [1] -> https://lore.kernel.org/lkml/20180626162615.19194-1-nm@ti.com/ Patch series includes the following *) Merge pci-keystone-dw.c into pci-keystone.c so that we have single file for PCIe keystone driver. *) Cleanup the pci-keystone driver. In certain cases the DT binding is also modified since PCIe in keystone has never worked in mainline due to lack of PHY support. *) Included the PHY driver here for completeness (though the driver might go via linux-phy tree) *) Included the device tree patches here. Once this series is reviewed it'll be sent to be merged via Tony's tree. *) Patch to fix ATU identification for designware version >= 4.80 in designware core is also included here. TODO: *) Add Endpoint Support for AM654 *) Send a patch to fix the MRRS after the correct value is identified. Once this series is reviewed I'll split the series and send to corresponding subsytem Maintainers after removing RFC in subject. Thanks Kishon Benoit Parrot (1): arm64: dts: k3-am6: Add Main System Control Module node Kishon Vijay Abraham I (39): PCI: keystone: Use quirk to limit MRRS for K2G PCI: keystone: Use quirk to set MRRS for PCI host bridge PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() PCI: keystone: Do not initiate link training multiple times PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() PCI: keystone: Add start_link/stop_link dw_pcie_ops PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c PCI: keystone: Cleanup MSI/legacy interrupt configuration and handling PCI: keystone: Remove redundant platform_set_drvdata PCI: keystone: Use uniform function naming convention dt-bindings: PCI: keystone: Add bindings to get device control module PCI: keystone: Use syscon APIs to get device id from control module dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Use platform_get_resource_byname to get memory resources PCI: keystone: Cleanup PHY handling PCI: keystone: Invoke pm_runtime APIs to enable clock PCI: keystone: Cleanup configuration space access PCI: keystone: Get number of OB windows from DT and cleanup MEM space configuration PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode PCI: keystone: Cleanup ks_pcie_link_up() PCI: keystone: Add debug error message for all errors PCI: keystone: Reorder header file in alphabetical order PCI: keystone: Cleanup macros defined in pci-keystone.c PCI: keystone: Move initializations to appropriate places dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Document "atu" reg-names PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 PCI: keystone: Add support for PCIe in AM654x Platforms phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC phy: ti: Add a new SERDES driver for TI's AM654x SoC ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its arm64: dts: k3-am6: Add mux-controller dt node required for muxing SERDES arm64: dts: k3-am6: Add SERDES DT node arm64: dts: k3-am6: Add Root Complex PCIe dt node .../bindings/pci/designware-pcie.txt | 7 +- .../devicetree/bindings/pci/pci-keystone.txt | 17 +- .../devicetree/bindings/phy/ti-phy.txt | 77 ++ MAINTAINERS | 2 +- arch/arm/boot/dts/keystone-k2e.dtsi | 15 +- arch/arm/boot/dts/keystone.dtsi | 18 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 142 +++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pci-keystone-dw.c | 484 -------- drivers/pci/controller/dwc/pci-keystone.c | 1059 +++++++++++++---- drivers/pci/controller/dwc/pci-keystone.h | 57 - .../pci/controller/dwc/pcie-designware-host.c | 16 - drivers/pci/controller/dwc/pcie-designware.c | 50 +- drivers/pci/controller/dwc/pcie-designware.h | 13 +- drivers/phy/phy-core.c | 6 + drivers/phy/ti/Kconfig | 11 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-am654-serdes.c | 513 ++++++++ include/dt-bindings/phy/phy-am654-serdes.h | 13 + 21 files changed, 1690 insertions(+), 816 deletions(-) delete mode 100644 drivers/pci/controller/dwc/pci-keystone-dw.c delete mode 100644 drivers/pci/controller/dwc/pci-keystone.h create mode 100644 drivers/phy/ti/phy-am654-serdes.c create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h -- 2.17.1