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[209.132.180.67]) by mx.google.com with ESMTP id w21-v6si14129530pgv.462.2018.06.19.06.41.07; Tue, 19 Jun 2018 06:41:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b="pIl/770u"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937691AbeFSNlE (ORCPT + 30 others); Tue, 19 Jun 2018 09:41:04 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35003 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937635AbeFSNlB (ORCPT ); Tue, 19 Jun 2018 09:41:01 -0400 Received: by mail-wm0-f66.google.com with SMTP id j15-v6so565595wme.0 for ; Tue, 19 Jun 2018 06:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=BbgokXtJGDozTTd+Fk8mX44LvySHxUpDGzkdC0ZqN90=; b=pIl/770uM+0iLWbzWd9GIY9rV+c5mMp3vXOS5DCy7OOm/I+/cNlM8aDXH3ahsZDbhU /7EHAFgiCmud7GG73Ga58AFkhfyqLb3pruYBqzHmdL5o5eYjusM9V+PFNuXi9RRAsK2b Rt3oJtdOj8/1GWdJcRLpPxQ3zi958YfVHuqbbM6J+kG5I49VdwvxwOlu79OBuYFWRxPu KhlAbaeg/lTeJgANTrhxFZq7kwZ3xdmlK02UMnz80ivCNd6OP4j/d6+8DkZPl8x6sYLS wA7nIKMhU3ZBaAnXAdfdReKmtN6LfpZ89mP5G3YS4zuMqO6eGBHb8BxX/mj2e1wgPbfe gcvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BbgokXtJGDozTTd+Fk8mX44LvySHxUpDGzkdC0ZqN90=; b=OVYbgsJeAkqT5nuGLnKMvq74gFdPw9+YvxmxcTqPOphNh4+gCtdZNB0YTT3HNxZUnL cv5Xl2puDs1nGkfQC9+PNxyNMEjXG/Wio3WGyNgkf/bqSh57bnt5PHNyDlpenFa8otl7 8jj5wWJtrAVQBx7tUGROPRvmImGwy1VBYdroAxJYdfP35XdMwzPeb/YyRDrAGDWZY4zS I+rohT6+PAKskrwhxRuJFkoOpi7m6E4KQEfITZVallYsC51NJRM2vq91lq31Cg3kSfGd JVJSPqmGp8bLG5ilF//bS3Q6n9LIfxLElK83UkZrXsEvcKqSG6bzy9zEOwVAWpPN+izo +mdQ== X-Gm-Message-State: APt69E2ehKSLnoIiWgphWkA5uATeFVCg5fQdqlQs3VByZvi1L5iBxTNK 9SiiZ6bbr3xHurUGZnrKEeslBDG2 X-Received: by 2002:a1c:4a06:: with SMTP id x6-v6mr7665924wma.89.1529415660432; Tue, 19 Jun 2018 06:41:00 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id t10-v6sm17196154wrq.74.2018.06.19.06.40.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Jun 2018 06:40:59 -0700 (PDT) From: Jerome Brunet To: Michael Turquette , Stephen Boyd Cc: Jerome Brunet , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-soc@vger.kernel.org, David Brown , Andy Gross , Linus Walleij , Quentin Schulz , Maxime Ripard Subject: [PATCH 0/2] clk: enforce CLK_SET_RATE_GATE along the tree Date: Tue, 19 Jun 2018 15:40:49 +0200 Message-Id: <20180619134051.16726-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a resend of the last unmerged patch of the clock protect v5 [0] patchset. It makes use of the clock protection mechanism to fix and enforce CLK_SET_RATE_GATE flag. With this flag set, any operation resulting in a rate change or glitch should be prevented. This might be useful when, for example, a PLL can't safely relock while in use. ATM, this is enforced only on the leaf clock of the operation (the clock on which clk_set_rate() is called). It is ignored otherwise. It means that, if: * clock A has CLK_SET_RATE_PARENT and is a child on clock B * clock B has CLK_SET_RATE_GATE set it is possible to: * call clk_prepare_enable on clock A (clock B also gets enabled) * call clk_set_rate() on clock A, => with rate propagation clock B (or its parents) might change while enabled Patch 2 of this series fixes this problem. Some platform may have been relying on the broken implementation of CLK_SET_RATE_GATE but, since the platform actually bypassed CLK_SET_RATE_GATE, we can drop the flag without changing anything. This is the case for qcom SDC clock and mmci driver, which does the following sequence: * clk_get() * clk_prepare_enable() * clk_get_rate() * clk_set_rate() This is obviously not possible when CLK_SET_RATE_GATE is set. Patch 1 drops the CLK_SET_RATE_GATE from qcom sdc clocks. Other qcom's clocks are using the same scheme, so maybe there something worth checking here. This case was detected using kernelCI but some other platforms might be doing the same. Maintainers of the platforms using this flag have been warned ... but please test! [0]: https://lkml.kernel.org/r/20171201215200.23523-1-jbrunet@baylibre.com Jerome Brunet (2): clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks clk: fix CLK_SET_RATE_GATE with clock rate protection drivers/clk/clk.c | 16 +++++++++++++--- drivers/clk/qcom/gcc-ipq806x.c | 3 --- drivers/clk/qcom/gcc-mdm9615.c | 2 -- drivers/clk/qcom/gcc-msm8660.c | 5 ----- drivers/clk/qcom/gcc-msm8960.c | 5 ----- 5 files changed, 13 insertions(+), 18 deletions(-) -- 2.14.3