From patchwork Mon Apr 16 17:57:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 133482 Delivered-To: patch@linaro.org Received: by 10.46.84.18 with SMTP id i18csp3839946ljb; Mon, 16 Apr 2018 10:57:54 -0700 (PDT) X-Google-Smtp-Source: AIpwx48PMSbki6iuMRcSfsH0KbT/qNOQO6ceCJ7bu6GfNAAJybhEDU2FRX4hLU6esr2WdNnZsvBY X-Received: by 2002:a17:902:e01:: with SMTP id 1-v6mr5166627plw.211.1523901474117; Mon, 16 Apr 2018 10:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523901474; cv=none; d=google.com; s=arc-20160816; b=lq3VHlCCl+ed+3frk4Qs4TM2alvZoc/L97AxvcH7mUdShJHbjm4xlWZ/5WkwhvWjA1 NZaOWtLIGJXa+PzVkBcX9isnuGVUCTvOMZhXE1LQBxdl5h6HRnSr4lEsGBipTDT71Sq7 pErE65MdGHoEGNycBsqZB+IagrTwBwFtkSncb+VVx3STdXk3SFIDtsBtXz4pKtZknYcR SXaD4IRWryCLf8Fpp4a2DM/dtBEZpV4ONJQ9Pod76eAzRAUbqy35rR3oj8HThDJNI5hG 12U2wrjYfXXRb1CaZBqj8Puh3WlLK8FaZTLXDd3eEutzo81EAHkMcuL1M8Sx9x2FZoqk sCrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=MNkTmKANCzqxxGd+pd2jjWOUFpLHC+BLUc+QCWeuuos=; b=B9rZv6La7pPwW++VIy89wrZwwOWTfCGH2Qftjsm1gNtaX8KsTkCEd+1ffJF5TrtkTs vxST6Q+R7pliMHXoCjvZMQEbyvk0HVT9lDpsdgJpyRLuKCtU5Lh2nCSFr8ljMCbvug4a r9bGc+zgfYWL5rC3X4aXiHhrpYB5bOHoXPuF3k7/CMmhco6Ayh8JeO4MZgFfv/RSrWuU 9eG05J+1HpsvRzGUuSi8r4ixZX6znUNqgl70DRkC+TukndbkY24H7akStihyzegFPpSc JR2DmlauLEZgfV0tF+USQU0Fo+D7KU22tSSE6FRFpaDfjMNmnk17WH94dCIDJg1oRO9B LfIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=sAYXF048; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g186si5555098pfb.76.2018.04.16.10.57.53; Mon, 16 Apr 2018 10:57:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=sAYXF048; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753168AbeDPR5v (ORCPT + 29 others); Mon, 16 Apr 2018 13:57:51 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:40043 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751135AbeDPR5s (ORCPT ); Mon, 16 Apr 2018 13:57:48 -0400 Received: by mail-wr0-f194.google.com with SMTP id v60so24570655wrc.7 for ; Mon, 16 Apr 2018 10:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=MNkTmKANCzqxxGd+pd2jjWOUFpLHC+BLUc+QCWeuuos=; b=sAYXF048+y5BYD5gsVZf4FcV5KOpPjkm8NcMqlqud7Wh5XYXMq5ZZez0Exo4vIiN6i S4W2zTmgLrw5JVMW3gWPWUCJwFtupfOgG4KM/3QD/R8Ob8wSH8JQr/pkutuuKTVXM4N6 F/A2Uz4bbWeU2FJ9pKTSLA39F8eH1rAxzBqMN1r+ZsaceAAhylNIfCzVRWLw9yzTMO5U 52I2K1a4GXA/SHwyaiV1VAXArGs0tbNrJL8WxuntpsVBXUnaLk1zZcZQMdG261LB5mTN MBWhXC9/f04LLKs185XO5bvEo5r+Kg/vbyAqIdgLCIATp8cYfFpVLRIk0tvwAxxCViM0 lybQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MNkTmKANCzqxxGd+pd2jjWOUFpLHC+BLUc+QCWeuuos=; b=pEJ8vx3qi83+RYpNhIo7+nQ+jGPPgcCKx2w8TOS5AtAaIsZL/IG98VGxYVODRZTch2 5OHQDYOpxuVYlVWW7AULEUpWrC9xmi+SHXNtzOhApeIzr7YxDk5Og0YwdjPuWX68KlH3 ft4UnDeA+uLQCdgg321RxxifngYGmbFJlxk9tuR4Ix42OWpfJLg91bwBCaJVwncmvRdD LXt5HEd+zle5KCxpOe63lkao9SFXU9eMKJgTsfVANgTSm8u2+OIx5m0/KTncVLFB1zI+ F1QTm/iqvA8iIzTopSjIkSoFRO3VcwV/SRVDMPw0jmot2VuVlUdzL8JVN0BM7HzSGGIl QFug== X-Gm-Message-State: ALQs6tBs7vJojLZK/MA3EkZ73PIi2LTmHYLzSIqmrvN+br3mk8t0Wn6i XJsaNKey0+kC96t2TKSAoESNiAan X-Received: by 10.223.130.72 with SMTP id 66mr5650629wrb.127.1523901467317; Mon, 16 Apr 2018 10:57:47 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 24sm18967123wrt.60.2018.04.16.10.57.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Apr 2018 10:57:46 -0700 (PDT) From: Jerome Brunet To: Michael Turquette , Stephen Boyd , Russell King Cc: Jerome Brunet , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/3] clk: add duty cycle support Date: Mon, 16 Apr 2018 19:57:40 +0200 Message-Id: <20180416175743.20826-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset adds the possibility to control the duty cycle ratio of a clock within the clock framework. This useful when the duty cycle ratio depends on another parameter controlled by the clock framework. For example, the duty cycle ratio may depends on the value of a divider (ratio = N / div). This is also useful if the related clock is part of large tree. In this case, using CCF to control the clock tree and the PWM framework for the duty cycle would be a nightmare for the provider and the consumer. A clock provider is not required to implement the operation to set and get the duty cycle. If it does not implement .get_duty_cycle(), the ratio is assumed to be 50%. This series also provides pass-through operations ready to be used for clock which don't resample the clock signal (such as gates and muxes). This is provided to make things easier for consumers. Clocks are usually made of several elements, like a composite clocks with a mux, a divider, and a gate. With the pass-through ops set on the gate, the consumer does not need to be aware that the duty cycle is actually controlled by the divider, it can continue to use the clock through the gate, as usual. The simple propagation will stop at the first clock which resample the signal (such as a divider). Patch 2 and 3 add the pass-through ops to the generic gate and mux ops. In this first version, it is unconditional, but maybe we should provide a flag to let people decide what is best for them ? The series has been developed to handled the sample clocks provided by audio clock controller of amlogic's A113 SoC. To support i2s modes, this clock need to have a 50% duty cycle ratio, while it should be just one pulse of the parent clock in dsp modes. PS: Checkpatch complains heavily about the white space in the trace header file. I believe I have respected the style already used in this file. Please let me know if it should be done differently. Jerome Brunet (3): clk: add duty cycle support clk: gate: add duty cycle passthrough ops clk: mux: add duty cycle passthrough ops drivers/clk/clk-gate.c | 2 + drivers/clk/clk-mux.c | 4 + drivers/clk/clk.c | 196 +++++++++++++++++++++++++++++++++++++++++-- include/linux/clk-provider.h | 17 ++++ include/linux/clk.h | 32 +++++++ include/trace/events/clk.h | 36 ++++++++ 6 files changed, 282 insertions(+), 5 deletions(-) -- 2.14.3