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[209.132.180.67]) by mx.google.com with ESMTP id s3si15687107plp.433.2017.12.21.18.45.50; Thu, 21 Dec 2017 18:45:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=XFV6gkMw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755690AbdLVCpm (ORCPT + 28 others); Thu, 21 Dec 2017 21:45:42 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:40724 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755367AbdLVCpj (ORCPT ); Thu, 21 Dec 2017 21:45:39 -0500 Received: by mail-pl0-f65.google.com with SMTP id 62so10714586pld.7; Thu, 21 Dec 2017 18:45:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=yWSlJlQSbdMrKzmQlMS51SwHMGdGI4znFjrt0fFfZmY=; b=XFV6gkMweepXQpZ7oA5TttuoagzLVl3WSNSR1HfeuiP/SXy52238pR0X3o2OU085vg WET2oGr0qFaPylCnMfVUD4fzKfIY+62Assw54KiEc5PZKB9DZCoVgngg88tAOuTxAms2 E9qjdQwEsloeb6UfOywXeL+tU2xsDQzfxoeIRQGXzjjgpdJjh3wBWwN4h3Ix8eOUk/7z Y1voMQKO1mnN9Hjz71gj9pyEY0+9irWhyEXarvJUujD5kFlRiR3ZcaPsuLpYVKKJpZO4 P46vNMYLR+CpF5rAiKpItszHO9HxIwjPSOzSlDjNw+AIA7SMXuDn/F8yOCKuDRGEuUPg yNhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=yWSlJlQSbdMrKzmQlMS51SwHMGdGI4znFjrt0fFfZmY=; b=EV8d3h6lqtE8DpiRwlyIrPIsRmwx2L4MFGdG3aF6wLJ5P2dZbbkqLP140fJJFYu2BV ez2o3h/aEP4Np2IwRCuBe7jWx7r6QUD3bxyaegFpNpAhcEFI6ih9Kdqh8A1xlNE2lUtS WJmEl6P56h8p3SWOSGzQqqNU0eeab2dilCOcGrbN91bn20j0CdWkN05kSsD9l9iWJm1C 6CcJYQ9BujWWF/45gPNsiuI6iH8ZjOAAj2h5uEVqcvjx+8ljKXINYgcIrb7LYdG08Ian U8KdJKKkBhr7e+Sor1oIt8wge/Y/PUsrGUF5y13qTtmFnL1gL0gHy+5+VnpgSwnxjXmr dV7A== X-Gm-Message-State: AKGB3mLTRGypWMTpxpjpweNGxMH8y5cuCzOM+sz99N8yGkyd6QriAaId D1RXvcOjotL8B3B88g+7YQc= X-Received: by 10.84.172.195 with SMTP id n61mr12281572plb.321.1513910738101; Thu, 21 Dec 2017 18:45:38 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id z2sm34658478pgu.17.2017.12.21.18.45.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Dec 2017 18:45:36 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 22 Dec 2017 13:15:27 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v7 0/5] clk: Add Aspeed clock driver Date: Fri, 22 Dec 2017 13:15:17 +1030 Message-Id: <20171222024522.10362-1-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. Clk maintainers, this patch set requires this signed tag to be merged first: git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git tags/aspeed-4.16-clk-binding It contains a single commit on top of 4.15-rc1 that will also be merged via the ARM SoC tree. It has been reviewed by Arnd and Rob. This is v7. See patches for detailed changelogs. v7: Address reivew from Stephen and device tree changes v6: Added reviewed-bys v5: Address review from Andrew v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 658 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 671 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c -- 2.15.1