From patchwork Thu Dec 7 12:57:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 120969 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8331242qgn; Thu, 7 Dec 2017 05:07:13 -0800 (PST) X-Google-Smtp-Source: AGs4zMZQN7jtL7eWsESHsX+Sq+0qXfb6R8UHRqnutfE8HVLDjDvv6SltKVlDLWNFF6UMnEtSy42Q X-Received: by 10.99.112.89 with SMTP id a25mr24931947pgn.2.1512652033690; Thu, 07 Dec 2017 05:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512652033; cv=none; d=google.com; s=arc-20160816; b=qbxSqGTUiilpNMFD7jlviT+GfGLWN6MYw4JyGbc0q73RLPiYBM1s/AaHcQ1Vgii8EN +DETyEte06EQFCMND2NoP5F9b6fDkaxLZkZzUl232RUyJZR/wVBKb7ivLiLpjmFNglfY gSqPScGGNiV5u8uT+CiWQpQQNnjXIlfYlHkDHcicasusFGP4YBrhhisg6f4OAwHl6A2Y U4CO1uVk7ZQFISQHHfH/j1wA7sElhNPD/JRHMTL3uIK1CXkQ1PUvMjjSiRR45U+O4DNa D5vEZkeAjrtwsDgHxhoOpXYSoUeP3lsL/LMi0j1VKfLQn7VgrZfP9wUeNClAHygy7NOd NOOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=fsHzzKHu+k3hiOk/hYFAJnBhTWCqYOLopxl3GVAL0Mk=; b=nae+pOerZoGI0y1ty2Hn+M3nM1crKkSrDR2JOPlp/pMSOCp4sA3r2ZwvSQCZsUTYTs cXTxt2Is2Ey/7muOB4e2pzrcbXu5jS+sn7LFBBWC73eU9Z2KwBWMt7gNtgxDcAonQ1pK JSn7cTKVYA3yZKZutZt6aVtZh5QxrfhAO7zwTpHc+mBPsVaTt1mFmby4SSY1qvx6p51e TH9g6RIZXs3esoG0rjHE2XdtDPEiRPx9e83pzML/4KfAyDw9qrzAkoX2jfi2HJfbjA/l PwXhHQ6/oRFw6TQlqtk2rL1MFcmgcK52uEY2X8NIbEbOqq3hf1u83N0b9/7cNFJGK/Fn 8+lA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q6si3399880pgt.668.2017.12.07.05.07.13; Thu, 07 Dec 2017 05:07:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932117AbdLGNHM (ORCPT + 22 others); Thu, 7 Dec 2017 08:07:12 -0500 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:38647 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1754520AbdLGNDk (ORCPT ); Thu, 7 Dec 2017 08:03:40 -0500 Received: from ig2.spreadtrum.com (shmbx01.spreadtrum.com [10.0.1.203]) by SHSQR01.spreadtrum.com with ESMTP id vB7D2WXD069135 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 7 Dec 2017 21:02:32 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX01.spreadtrum.com (10.0.1.203) with Microsoft SMTP Server (TLS) id 15.0.847.32; Thu, 7 Dec 2017 21:03:27 +0800 Received: from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Thu, 7 Dec 2017 21:03:08 +0800 From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland CC: Catalin Marinas , Will Deacon , , , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Ben Li , Orson Zhai , Chunyan Zhang Subject: [PATCH V7 00/12] add clock driver for Spreadtrum platforms Date: Thu, 7 Dec 2017 20:57:03 +0800 Message-ID: <20171207125715.16160-1-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com vB7D2WXD069135 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This series adds Spreadtrum clock support together with its binding documentation and devicetree data. Any comments would be greatly appreciated. Thanks, Chunyan Changes from V6: (https://lkml.org/lkml/2017/11/27/217) * Changed to use "//" format for the file header * Addressed Stephen's comments: - Put the common macros in clk-provider.h instead of clk_common.h, also removed the same macros from sunxi-ng/ccu_common.h and zte/clk.h; - Removed CLK_FIXED_RATE(), and moved the fixed rate clocks from driver to DT; - Use devm_of_clk_add_hw_provider() instead; - Removed sprd_regmap_{read|write}(), use regmap API directly; - Removed all full stop on error messages. * Use IS_ERR_OR_NULL() instead of IS_ERR() for checking regmap pointers; Changes from V5: (https://lkml.org/lkml/2017/11/20/21) * Rebased the whole patch-set to 4.15-rc1; * Fixed kbuild-test warnings; * Switched to use devm_clk_hw_register() instead of clk_hw_register(); * Removed useless debug information from sc9860-clk.c. Changes from V4: (https://lkml.org/lkml/2017/11/10/30) * Added acked-by of Rob Herring; * Removed spin lock from Spreadtrum's gate, mux, div drivers, since we have switched to use regmap. Changes from V3: (https://lkml.org/lkml/2017/11/2/61) * Addressed comments from Julien Thierry: - Clean the if branch of sprd_mux_helper_get_parent() - Have the Gate clock macros and ops for both mode (i.e. sc_gate and gate) separate; - Have the Mux clock macros with/without table separate, and same changes for the composite clock. * Switched the function name from _endisable to _toggle; * Fixed Kbuild test error: - Added exporting sprd_clk_regmap_init() which would be used in other module(s); * Change the function sprd_clk_set_regmap() to the static one, and removed the declear from the include file; * Addressed comments from Rob: - Separate the dt-binding include file from the driver patch; - Documented more for the property "clocks" * Changed the syscon device names; * Changed the name of 'sprd_mux_internal' to 'sprd_mux_ssel' Changes from V2: (http://lkml.iu.edu/hypermail/linux/kernel/1707.1/01504.html) * Switch to use regmap to access registers; * Splited all clocks into 16 separated nodes, for each belongs to a single address area; * Rearranged the order of clock declaration in sc9860-clk.c, sorted them upon the address area; * Added syscon device tree nodes which will be quoted by the node of clocks which are in the same address area with the syscon device; * Revised the binding documentation according to the dt modification. Changes from V1: (https://lkml.org/lkml/2017/6/17/356) * Address Stephen's comments: - Switch to use platform device driver instead of the DT probing mechanism. - Move the common clock macro out from vendor directory, but need to remove those overlap code from other vendors (such as sunxi-ng) once this get merged. - Add support to be built as a module. - Add 'sprd_' prefix for all spin locks used in these drivers. - Mark input parameter of sprd_x with const. - Remove unreasonable dependencies to CONFIG_64BIT. - Add readl() after writing the same register. - Remove CLK_IS_BASIC which is no longer used. - Remove unnecessery CLK_IGNORE_UNUSED when defining a clock. - Change to expose all clock index. - Use clk_ instead of ccu. - Add Kconfig for sprd clocks. - Move the fixed clocks out from the soc node. - Switch to use 64-bit math in pll driver instead of 32-bit math. * Revise binding documentation according to dt modification. * Rename sc9860.c to sc9860-clk.c Chunyan Zhang (12): drivers: move clock common macros out from vendor directories clk: sprd: Add common infrastructure clk: sprd: add gate clock support clk: sprd: add mux clock support clk: sprd: add divider clock support clk: sprd: add composite clock support clk: sprd: add adjustable pll support dt-bindings: Add Spreadtrum clock binding documentation clk: sprd: Add dt-bindings include file for SC9860 clk: sprd: add clocks support for SC9860 arm64: dts: add syscon for whale2 platform arm64: dts: add clocks for SC9860 Documentation/devicetree/bindings/clock/sprd.txt | 63 + arch/arm64/boot/dts/sprd/sc9860.dtsi | 115 ++ arch/arm64/boot/dts/sprd/whale2.dtsi | 62 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sprd/Kconfig | 14 + drivers/clk/sprd/Makefile | 11 + drivers/clk/sprd/common.c | 96 ++ drivers/clk/sprd/common.h | 38 + drivers/clk/sprd/composite.c | 60 + drivers/clk/sprd/composite.h | 51 + drivers/clk/sprd/div.c | 90 + drivers/clk/sprd/div.h | 75 + drivers/clk/sprd/gate.c | 111 ++ drivers/clk/sprd/gate.h | 59 + drivers/clk/sprd/mux.c | 76 + drivers/clk/sprd/mux.h | 74 + drivers/clk/sprd/pll.c | 266 +++ drivers/clk/sprd/pll.h | 108 ++ drivers/clk/sprd/sc9860-clk.c | 1974 ++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_common.h | 29 - drivers/clk/zte/clk.h | 18 - include/dt-bindings/clock/sprd,sc9860-clk.h | 404 +++++ include/linux/clk-provider.h | 38 + 24 files changed, 3785 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt create mode 100644 drivers/clk/sprd/Kconfig create mode 100644 drivers/clk/sprd/Makefile create mode 100644 drivers/clk/sprd/common.c create mode 100644 drivers/clk/sprd/common.h create mode 100644 drivers/clk/sprd/composite.c create mode 100644 drivers/clk/sprd/composite.h create mode 100644 drivers/clk/sprd/div.c create mode 100644 drivers/clk/sprd/div.h create mode 100644 drivers/clk/sprd/gate.c create mode 100644 drivers/clk/sprd/gate.h create mode 100644 drivers/clk/sprd/mux.c create mode 100644 drivers/clk/sprd/mux.h create mode 100644 drivers/clk/sprd/pll.c create mode 100644 drivers/clk/sprd/pll.h create mode 100644 drivers/clk/sprd/sc9860-clk.c create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h -- 2.7.4 Acked-by: Philippe Ombredanne