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[209.132.180.67]) by mx.google.com with ESMTP id o7si9330786pgr.606.2017.10.29.23.03.14; Sun, 29 Oct 2017 23:03:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=INALUON0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752181AbdJ3GDL (ORCPT + 27 others); Mon, 30 Oct 2017 02:03:11 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:44783 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750931AbdJ3GDJ (ORCPT ); Mon, 30 Oct 2017 02:03:09 -0400 Received: by mail-pf0-f193.google.com with SMTP id x7so10175475pfa.1; Sun, 29 Oct 2017 23:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=P8aM51pjDx6CGdNtwKl5ImauPPHvledUPCl7EcH+6og=; b=INALUON0+gHGMSEbuUCgdDpHfrhqjes5z7RU77V8vkLhoERyB2JY50eq17wLs+NNwG S5aCAa6hyf+ZK2f5ZFvDdOcl6e+iH/O4540XsQ6jC+SrDD4nymE2o5UBjCL+mhwIw12V 4OsWY553S9anLY5rjkAkIQwN0naDbB2qAOiqZTSowruSVbOjm333dTrOnMxJiGR+x5Zx WPJ7RefzABOhik9sEUOZaMh/mLk8fpj6IUq/1zmbZVycxn71eE4d6rn51EKFwQYg74hM SWv75kgpf3CEMOcRg/OayqxOhZvNhZ7KfXlqTsZKi+YQ9JabMK0BJkz93quzC8+Jd0xM c1FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=P8aM51pjDx6CGdNtwKl5ImauPPHvledUPCl7EcH+6og=; b=KTQ6JHq4VyWrIURNwThGAEalbbNZ4Y+uOtvtl07ccoNy/zRWyH5Z9KwQPHp9qdsdvV hUYReF/62I9WfyUHeMjocXAJcK/NCLKTsrXVHLUDU1diVuDhRDbwC494h6QoQp93Qhno JmCAKQlnXJm6FjNDLtwnjsP5oc9JVdE8Ce0MGYNbg7Oh2SCOE8zdCqsnrz3+1IA4uMfK +eQX+yrM3QPZm1qioisK+9LbDh4Vi7k2gtGYhZ73fZk1dMLIG/aY5rXDVMLX2qpKUWFA Aj6TykvoAlQDyLdnmuPLxcCpe1BytuUKRoJPVa1yC0p7Px5pRb7Yx46Zt0Rb4U2OxLOB d6Gg== X-Gm-Message-State: AMCzsaX92oCbYf9EKtTdNA4h2+k8j3deQ3iQYMN0SVtu17B+E8but3PF 6bcY6nRlNHK5Aq3YcVHnWdI= X-Received: by 10.84.244.12 with SMTP id g12mr6534375pll.223.1509343389059; Sun, 29 Oct 2017 23:03:09 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id p21sm26311345pfk.185.2017.10.29.23.03.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 29 Oct 2017 23:03:07 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 30 Oct 2017 16:32:59 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v5 0/5] clk: Add Aspeed clock driver Date: Mon, 30 Oct 2017 16:32:45 +1030 Message-Id: <20171030060250.701-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is v5. See patches for detailed changelogs. v5: Address review from Andrew v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 666 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 731 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1