From patchwork Tue Oct 3 06:55:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 114660 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1540413qgn; Mon, 2 Oct 2017 23:56:12 -0700 (PDT) X-Received: by 10.84.185.106 with SMTP id e39mr15968426plg.333.1507013772314; Mon, 02 Oct 2017 23:56:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507013772; cv=none; d=google.com; s=arc-20160816; b=aEn3n9sU45cOnjPgtnW2u3z9p4wVw68PdRYZ8b4jxqPadqHWSJncLMwXyUetHAgwf+ eJD+MJFPLKq+hWfIdxeDXfbgC0EU59u1DKo9eXSOd0hXqZIZ89g6VcvAvTeTbkN2jOJH jKB8siyjGjE/DA3tKkgV8tblrVrfdR16qV8buMSalPsT9IMErQ9w5ddPTmAo9NvY228S wklKf7hFq1rsKUBEdF5BKqFRM/i//ZdW62NvBcOfHC1H7z6Dd3NK8t6fzZbsx12dTHI5 53kQVmLad1ccVEJJuyaV2aZi9SaUpYINQV3orz7JXeiziR+DOGxHcfm2d4o4roiS00eL YAXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=G6EJXhw5IiX7bkzbqRB1CUohpxV+4ML+fJBPnIOURK0=; b=tSlO6JPZzpDDs/ZTh+JpWu1qDz351oImRLqFHEXnx1rybE5ytEEm6MtjR5xl4nYc13 hnt4vpvvYrcIgjyXNRlk23AENNwd0ZGGDaRfMWzu1pC7kDFk08XtM60ayCy/1Wt8r50X O8QsdFXYLjyVqKr5K9RS6xAlmb+viJ8Dm1FEZU7ofdwzdsxQNuoT3NG2WP8FlnsBRslS JYEeQgKyuEd1qZCxJL1097I3n1wI5B6FRS7Mx6hWiz/uvf68gbxcn/2hLsXnuDkygzyh OVLdzEdToBflBu0HNPYUxDx1CYsSA7TEczz5DwLJ4p+7zyV/4UdCswnL2F/9vrwhBDa/ 33Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=k5LZm+Of; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m6si9463167pgm.670.2017.10.02.23.56.12; Mon, 02 Oct 2017 23:56:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=k5LZm+Of; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751104AbdJCG4J (ORCPT + 26 others); Tue, 3 Oct 2017 02:56:09 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:33201 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750720AbdJCG4I (ORCPT ); Tue, 3 Oct 2017 02:56:08 -0400 Received: by mail-pg0-f66.google.com with SMTP id u136so8642989pgc.0; Mon, 02 Oct 2017 23:56:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=G6EJXhw5IiX7bkzbqRB1CUohpxV+4ML+fJBPnIOURK0=; b=k5LZm+OfdoZ9YGyZVG7sKuzMOSCGelIZ8egzdrfrgppANGA5pH5yD18EzROuI8I5cQ TbWdicjPh6tRTtfRlR+PbQWRgR/tIJyBjUNYFQDIPi06++qvu13+NtUIWfG0Rmw5bBG7 rcDS7es42HDheayuivyD39ZQHvqY/F8onOe9mQXGbneydivMTT4w65kXIN/8Ohf5B8uF 0Qz2flIgW7QpehqD6BXdEzkbdRq+3f4glOa5+fpsXO48vf0/2JXa4dFtlLiuyTlS8ksl Bh9oPnWKjWJDKQUqgNSBJLbp6uyTW6C92W3uuu1tTsfRhmvNz4MaUKIIJtd1yzbd7haQ 66zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=G6EJXhw5IiX7bkzbqRB1CUohpxV+4ML+fJBPnIOURK0=; b=SYTXuxYo24QO4YlLGUJvk47TFB3V2x6Y0ZTrHrJ4fdRr8ycjzOih3+9k2FxVKUF2ef lwTZaEG+WPiGGucDiOhoDAFj3eOT8PqpsP38BmNHPkWtZctfigM+93sSRxYVRpNEjIf2 8h6J26Yxsr2K4yyplAfkMgz6zdGG9evWBS7fvE9VNWCKH4jzti0v2HqejAUrFPY0LmNh Sv4+LoEap9cK0jRmju+K+EXAq+NSdf2PlA+qBrGGnhLYCSvn1gXDx5dE9AcHDccTSFR1 tVcHaoYtdhZ7Nh76/LyLg4BOs7BvFuBn5KZL2za4mI23Ln6SISOeNSIrXBnzIPuQ15HG lRtg== X-Gm-Message-State: AMCzsaUPE0byTMQkv3AYo+m46Oq8ETboFqZ90IWlNvb3eVv1V83qidM2 v77khbSb0wPlDohOh7AQ89s= X-Google-Smtp-Source: AOwi7QCy+SHy2rz6lTOWprxooRHCI7dW8hTSCTW3vQx9YLJ65gkaAofbG1rkffmh7dsFvHpmiMLNQw== X-Received: by 10.98.71.132 with SMTP id p4mr300846pfi.274.1507013767335; Mon, 02 Oct 2017 23:56:07 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id e66sm18685273pfe.79.2017.10.02.23.56.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Oct 2017 23:56:05 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 03 Oct 2017 17:25:57 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v4 0/5] clk: Add Aspeed clock driver Date: Tue, 3 Oct 2017 17:25:35 +1030 Message-Id: <20171003065540.11722-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is v4. See patches for detailed changelogs. v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 698 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 763 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1