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[209.132.180.67]) by mx.google.com with ESMTP id a17si605385pgf.385.2017.09.26.23.27.23; Tue, 26 Sep 2017 23:27:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=dqh9eFor; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751986AbdI0G1V (ORCPT + 26 others); Wed, 27 Sep 2017 02:27:21 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:33639 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750971AbdI0G1T (ORCPT ); Wed, 27 Sep 2017 02:27:19 -0400 Received: by mail-pg0-f66.google.com with SMTP id i130so8147902pgc.0; Tue, 26 Sep 2017 23:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=2Wx/okJehAVtVguJv1sE1UqJqcBg9Ok16/HIk0kZ8pU=; b=dqh9eFor2diPz6lIU51okPwwEzptyvQoP4cAn+ZIjCaI0dnMcsExyG9PLiqHExOEPr AnyXzOo+MEX6QYYfDD1zpdSCQ0wcUxOVnBlWJRX9/CDvncgxdHg2NojuQNrjN0McCsg/ j86jlJXzEfGixGkymxIanfvqMmfJKyvWTg3u5RhHhKc+tQxjsty1caJak32BduR8LqxU 2RhnDGijhET6itPYpILAnHnztn0WmKdvuCoBcRVCdUNRiPu3XkEbPY2beMi0fUWN9QyH ye1+G7b5BRQUYVnWyolgFKU3vtQ7tpB6RpIABp7zqb/ls5aY0+OuHCeRden5yJ6joXg6 Pl6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=2Wx/okJehAVtVguJv1sE1UqJqcBg9Ok16/HIk0kZ8pU=; b=PCXb4/Ti7PA+zk81DkmhPsgJIzbmKbU/ThwxOX1prHOEbPgVaAdgzyfr0X7ZPEw7GI 49HuQDd9ibwgLMEAO4FvX/d/Q8ZXeIst5PvsHyESS6Q4lJReE4vEEPHg/Qavt+1Nq0Sj 6SI6BVPAdk99Ox0/a+gQfQvutxFn+WVNBk0ys/WtP5y96J9eF3+HEkV8NuO80/QPra6S bjhA6M6lO4AN4QnQ7WIqIklqh/OZXMSGuF8VOPk1ufA5NFd54HjRCGrddpf9CFjLp8aO 3Aitl0YpbFqc5mZeBavaixcoTnVXSwF1iC77pZC8AWi5EI7Z0Ei6fmMqWQiqWJUxHW77 Svvg== X-Gm-Message-State: AHPjjUiFESq7HbYbR8pgGDqEShvLlP850VNuKTsqjMj7a4z/e9P90G9g cm6yMjv8Ko0kwdbcaFqAS2g= X-Google-Smtp-Source: AOwi7QD74f1gdlP01guNqkQ6oAqZlTuo2hYwBZSGQhSm/gwJg/ptw5EcI6r7HMCkjY0hzpN/pKqj8g== X-Received: by 10.98.12.19 with SMTP id u19mr348615pfi.143.1506493638637; Tue, 26 Sep 2017 23:27:18 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id e185sm19571080pfg.142.2017.09.26.23.27.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2017 23:27:17 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 27 Sep 2017 15:57:09 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v3 0/5] clk: Add Aspeed clock driver Date: Wed, 27 Sep 2017 15:56:57 +0930 Message-Id: <20170927062702.11350-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is version three of the series. Version one contained two patches; an update to the binding document and a single patch for the driver. Lee has merged the bindings change, so that is dropped from this series, and I split the driver out into a series of patches to make them easier to review. Version three addresses reivew from Andrew and has seen more testing on hardware. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infra spruce, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 654 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 719 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1