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[209.132.180.67]) by mx.google.com with ESMTP id x17si416304pfj.324.2017.09.20.21.27.11; Wed, 20 Sep 2017 21:27:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=COxhUbBC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751531AbdIUE1B (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:01 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:37479 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750930AbdIUE07 (ORCPT ); Thu, 21 Sep 2017 00:26:59 -0400 Received: by mail-pg0-f65.google.com with SMTP id v5so2780538pgn.4; Wed, 20 Sep 2017 21:26:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=BPdPjaKfibKDX6BMM7aYitnDy9shILco8CgqDu3wIEQ=; b=COxhUbBC14dFt/5PTmWQdvfYd1w49QXTVK+YS79080fhWg4jiz+8FO9Myp91RB9QF7 kiRBXnbWhUwIkl5hbGHPGriw/abWxHUZ2H2GDmoy3r9ZTgsMlUc3rRxvquLY90RV34e+ fvGkpNnZ7c978l0qRLQY8sJF+iKMoPN0X/e+ho3ps9JYcvc869ethaaHpd6ZeBQvAOSh ECVPzYjJ9jCJTUYKiAZ2DVQ7ypgPCrks7Zcu1csod/lIk8UzmKD0qHXnoRpE+zOWGbIu o/CL+LzwlT0Pwi50SI8T4pJXgkViy2DfZkU+VjEa8uN8Tq3cQm7G5lGTHypVJ2OfAPt6 cXbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=BPdPjaKfibKDX6BMM7aYitnDy9shILco8CgqDu3wIEQ=; b=t3rMrEWKTr6JpfNiDGSAD3d3iJrWsH7uFWxJ7jKUuYr0TuHuAqk594AmJmdRUCAGIU kX/A0AS3M7c+Tddx68LhmTQFErhG+azJ1ADGrS8CvZY7/jx+I09zj9oq6FMB1Nrse8iY UwBqKmkjfUQ7rP0oxnWexpzuYHo29FdAzZUO2BHMeUXfZGD+Liljj04y4g5PUuc1jcYZ wMq8OMuElqBp7ukgcDEnGsckaVmFYZ8rhtQEmSrdqcRBJb46zTIwlfj9uuZZofqxwsUz 0sR8o7MPujtGtftMBIBjBtKxrO8z6/tjiu2tveMwhDnahVWm9Em/O1hqxo10WkIw9Do8 8I2g== X-Gm-Message-State: AHPjjUjLFmSmIrtpxBkoeqLtXCz9L5uXQIb5FNbvomSA7ETXQY/giKDh oGEXnTt39WPrOrPWP6O/f98= X-Google-Smtp-Source: AOwi7QBM4IOOLj3HRGNvgmxBh888TZQPxzYATkmAeBlVjsXoRtfGgLXZvYnPoQ4al7+8vT3qimZnvg== X-Received: by 10.101.66.205 with SMTP id l13mr4365853pgp.278.1505968018842; Wed, 20 Sep 2017 21:26:58 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id a29sm643698pfj.88.2017.09.20.21.26.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:26:57 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:56:48 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 0/5] clk: Add Aspeed clock driver Date: Thu, 21 Sep 2017 13:56:36 +0930 Message-Id: <20170921042641.7326-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is version two of the series. Version one contained two patches; an update to the binding document and a single patch for the driver. Lee has merged the bindings change, so that is dropped from this series, and I split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infra spruce, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 645 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 710 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1