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[0/5] mmc: Add OMAP SDHCI driver

Message ID 20170821074132.4622-1-kishon@ti.com
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Series mmc: Add OMAP SDHCI driver | expand

Message

Kishon Vijay Abraham I Aug. 21, 2017, 7:41 a.m. UTC 
This is the first step in deprecating omap_hsmmc driver completely
and moving to sdhci-omap driver which uses the sdhci library.

This series adds a new SDHCI quirk to indicate MMC_RSP_136 has CRC (since
sdhci in OMAP has CRC)

Apart from the quirk, sdhci-omap has it's own callbacks
to set_clock (clock divider programming is different from generic sdhci)
, set_power, set_bus_width, set_bus_mode and platform_send_init_74_clocks.
These callback functions are implemented based on omap_hsmmc driver.

The sdhci-omap driver supports only the high speed mode and UHS/HS200
mode will be added in a later series.

It has been tested only in boards having DRA7 SoCs like dra7-evm, dra72-evm,
am571x-idk, am572x-idk, am57xx-evm. (Tested only eMMC and SD.
SDIO support will be added later). The plan is to fully convert DRA7
SoC to use SDHCI driver and then convert other legacy platforms to use
SDHCI.

Next Steps:
*) Add UHS support to sdhci-omap
*) Add SDIO support
*) Add support for older TI platforms

Changes from v1:
*) Remove the quirks and instead use sdhci_omap specific callbacks for
   set_power, set_busmode etc.
*) Add a patch from Adrian to tidy reading 136-bit responses

I've also pushed the entire series along with dependent dt patches @
https://github.com/kishon/linux-wip.git sdhci_omap_v1 (in case someone
wants to test)

Adrian Hunter (1):
  mmc: sdhci: Tidy reading 136-bit responses

Kishon Vijay Abraham I (4):
  mmc: sdhci: Add quirk to indicate MMC_RSP_136 has CRC
  dt-bindings: ti-omap-hsmmc: Document new compatible for sdhci omap
  mmc: sdhci-omap: Add OMAP SDHCI driver
  MAINTAINERS: Add TI OMAP SDHCI Maintainer

 .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   1 +
 MAINTAINERS                                        |   6 +
 drivers/mmc/host/Kconfig                           |  12 +
 drivers/mmc/host/Makefile                          |   1 +
 drivers/mmc/host/sdhci-omap.c                      | 629 +++++++++++++++++++++
 drivers/mmc/host/sdhci.c                           |  31 +-
 drivers/mmc/host/sdhci.h                           |   2 +
 7 files changed, 672 insertions(+), 10 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-omap.c

-- 
2.11.0

Comments

Ulf Hansson Aug. 30, 2017, 1:13 p.m. UTC | #1 
On 21 August 2017 at 09:41, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> TI's implementation of sdhci controller used in DRA7 SoC's has

> CRC in responses with length 136 bits. Add quirk to indicate

> the controller has CRC in MMC_RSP_136. If this quirk is

> set sdhci library shouldn't shift the response present in

> SDHCI_RESPONSE register.

>

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>


Thanks, applied for next!

Kind regards
Uffe

> ---

>  drivers/mmc/host/sdhci.c | 3 +++

>  drivers/mmc/host/sdhci.h | 2 ++

>  2 files changed, 5 insertions(+)

>

> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c

> index ba639b7851cb..9c8d7428df3c 100644

> --- a/drivers/mmc/host/sdhci.c

> +++ b/drivers/mmc/host/sdhci.c

> @@ -1182,6 +1182,9 @@ static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)

>                 cmd->resp[i] = sdhci_readl(host, reg);

>         }

>

> +       if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)

> +               return;

> +

>         /* CRC is stripped so we need to do some shifting */

>         for (i = 0; i < 4; i++) {

>                 cmd->resp[i] <<= 8;

> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h

> index 399edc681623..54bc444c317f 100644

> --- a/drivers/mmc/host/sdhci.h

> +++ b/drivers/mmc/host/sdhci.h

> @@ -435,6 +435,8 @@ struct sdhci_host {

>  #define SDHCI_QUIRK2_ACMD23_BROKEN                     (1<<14)

>  /* Broken Clock divider zero in controller */

>  #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN             (1<<15)

> +/* Controller has CRC in 136 bit Command Response */

> +#define SDHCI_QUIRK2_RSP_136_HAS_CRC                   (1<<16)

>

>         int irq;                /* Device IRQ */

>         void __iomem *ioaddr;   /* Mapped address */

> --

> 2.11.0

>