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[209.132.180.67]) by mx.google.com with ESMTP id h33si24580170plh.119.2018.12.22.15.36.13; Sat, 22 Dec 2018 15:36:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405041AbeLVXgI (ORCPT + 31 others); Sat, 22 Dec 2018 18:36:08 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:16650 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2392969AbeLVXgF (ORCPT ); Sat, 22 Dec 2018 18:36:05 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 024E98B3BF910; Sat, 22 Dec 2018 15:50:51 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.408.0; Sat, 22 Dec 2018 15:50:45 +0800 From: Zhou Wang To: Herbert Xu , "David S . Miller" , CC: , , Zhou Wang Subject: [PATCH 0/4] crypto: hisilicon: Add HiSilicon QM and ZIP controller driver Date: Sat, 22 Dec 2018 15:51:41 +0800 Message-ID: <1545465105-133138-1-git-send-email-wangzhou1@hisilicon.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds HiSilicon QM and ZIP controller driver in crypto subsystem. A simple QM/ZIP driver which helps to provide an example for a general accelerator framework is under review in community[1]. Based on this simple driver, this series adds HW v2 support, PCI passthrough, reset, PCI/misc error handler, debug support. But unlike [1], driver in this patchset only registers to crypto subsystem. There will be a long discussion about above accelerator framework in the process of upstreaming. So let's firstly review and upstream QM/ZIP crypto driver. References: [1] https://lkml.org/lkml/2018/11/12/1951 Zhou Wang (4): Documentation: Add debugfs doc for hisi_zip crypto: hisilicon: Add queue management driver for HiSilicon QM module crypto: hisilicon: Add HiSilicon ZIP accelerator support MAINTAINERS: add maintainer for HiSilicon QM and ZIP controller driver Documentation/ABI/testing/debugfs-hisi-zip | 50 + MAINTAINERS | 8 + drivers/crypto/hisilicon/Kconfig | 11 + drivers/crypto/hisilicon/Makefile | 2 + drivers/crypto/hisilicon/qm.c | 1823 ++++++++++++++++++++++++++++ drivers/crypto/hisilicon/qm.h | 177 +++ drivers/crypto/hisilicon/zip/Makefile | 2 + drivers/crypto/hisilicon/zip/zip.h | 60 + drivers/crypto/hisilicon/zip/zip_crypto.c | 410 +++++++ drivers/crypto/hisilicon/zip/zip_main.c | 1161 ++++++++++++++++++ 10 files changed, 3704 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip create mode 100644 drivers/crypto/hisilicon/qm.c create mode 100644 drivers/crypto/hisilicon/qm.h create mode 100644 drivers/crypto/hisilicon/zip/Makefile create mode 100644 drivers/crypto/hisilicon/zip/zip.h create mode 100644 drivers/crypto/hisilicon/zip/zip_crypto.c create mode 100644 drivers/crypto/hisilicon/zip/zip_main.c -- 2.8.1