From patchwork Fri Jan 5 13:12:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123515 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp800476qgn; Fri, 5 Jan 2018 05:13:11 -0800 (PST) X-Google-Smtp-Source: ACJfBouQ6NfOL7YZ8DB3juCR39dw1vBiG6qy/iAUE33ANxuagBMJOLCElcRleFTi8o3s8vmUTmb1 X-Received: by 10.159.244.3 with SMTP id x3mr3155313plr.192.1515157990967; Fri, 05 Jan 2018 05:13:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515157990; cv=none; d=google.com; s=arc-20160816; b=woGhezZEa9sg3/TOH04BqB2cxqX8vJmUONzfdZy7Jq4rX6V1XlTOG19IIX1sk9h4Pu JzsKJN+iDh25wFEwZZR2m0Kc29+x0EI1YjlyZmEi6rR5HiuhVWJSc5k7QCMMSY4SfMnm QWrNfuDeY/WES+dApIjBabaaIVwJl/OG0Papcl/MJpm0F3CRPMD90MFbZrexRzJCbeCQ t5KUXyN6rOCvsQBtyNdwMI306NnaHwk5ViCjWmW2Jic4N0x23g10QhonJfmRcR+lyIjo 7UONwG4HWcmf9GarG307X/xV90tpy4lpe4BXT9rvjN1nMR7s/+r5/oBNmwfTwAmB7gNO 3JHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=IxBVJRJF8kFV4xgy0O6SbwFyZfN5kk8gjLpe0ySRa4Y=; b=uNa4ThJ9ZXmeesRZGkJ+S0tyn60m9fS05qNWit2NxoVxHR+0068/9VmmbYn524FAfM xsRJ4GbCag+h4GtNiyQasnUgRCcYT47fFQFkZZAGduT7CCI2m5khL3nVRg8mEHItOMPC WCnNulyUrIBpQ44bPaUfgq0aJNmk2nV57cXWRmbxISuzN8YovUQSSrr5G78QRbEKB5pG lQ7+RiVAHpTNZszdc8klQFD7SPNtc3Ez/8yrnnhhaom5HKHOk8jMttXhPDZArYJZEVJ/ ceeOfar3MmQRTopm/Ci0N6amXkia4+/+HgNKh3QZrnoZTRzAwp9XwVZpDkoxMV+jo84o MEcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a2si4097383plt.229.2018.01.05.05.13.10; Fri, 05 Jan 2018 05:13:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751822AbeAENMp (ORCPT + 27 others); Fri, 5 Jan 2018 08:12:45 -0500 Received: from foss.arm.com ([217.140.101.70]:44722 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750837AbeAENMm (ORCPT ); Fri, 5 Jan 2018 08:12:42 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A44631529; Fri, 5 Jan 2018 05:12:42 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E77B3F53D; Fri, 5 Jan 2018 05:12:42 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id E14D91AE17B6; Fri, 5 Jan 2018 13:12:42 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, labbott@redhat.com, Will Deacon Subject: [PATCH v2 00/11] arm64 kpti hardening and variant 2 workarounds Date: Fri, 5 Jan 2018 13:12:30 +0000 Message-Id: <1515157961-20963-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi again, This is version two of the patches I posted yesterday: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/551838.html Changes since v1: * Added comment to BL/RET sequence in trampoline page * Removed writeback addressing modes from Hyp PSCI register save/restore * Avoid save/restore of x18/x19 across Hyp PSCI call * Always print message when kpti is enabled * Added tags Cheers, Will --->8 Marc Zyngier (3): arm64: Move post_ttbr_update_workaround to C code arm64: KVM: Use per-CPU vector when BP hardening is enabled arm64: KVM: Make PSCI_VERSION a fast path Will Deacon (8): arm64: use RET instruction for exiting the trampoline arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry arm64: Take into account ID_AA64PFR0_EL1.CSV3 arm64: cpufeature: Pass capability structure to ->enable callback drivers/firmware: Expose psci_get_version through psci_ops structure arm64: Add skeleton to harden the branch predictor against aliasing attacks arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 arm64: Implement branch predictor hardening for affected Cortex-A CPUs arch/arm/include/asm/kvm_mmu.h | 10 ++++ arch/arm64/Kconfig | 30 +++++++--- arch/arm64/include/asm/assembler.h | 13 ----- arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cputype.h | 4 ++ arch/arm64/include/asm/kvm_mmu.h | 38 ++++++++++++ arch/arm64/include/asm/mmu.h | 37 ++++++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 4 ++ arch/arm64/kernel/bpi.S | 79 +++++++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 116 +++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 13 ++++- arch/arm64/kernel/entry.S | 12 +++- arch/arm64/kvm/hyp/switch.c | 15 ++++- arch/arm64/mm/context.c | 11 ++++ arch/arm64/mm/fault.c | 1 + arch/arm64/mm/proc.S | 3 +- drivers/firmware/psci.c | 2 + include/linux/psci.h | 1 + virt/kvm/arm/arm.c | 8 ++- 20 files changed, 372 insertions(+), 30 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.1.4