From patchwork Wed Oct 18 11:00:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 116174 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5582752qgn; Tue, 17 Oct 2017 19:57:47 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDh4Mal2Lu0X835Okp0AkNdv5FGS5RhxPyovmunSZHSA2ymnWPg9hoiNjbxuC1zpFvUlBJR X-Received: by 10.99.129.199 with SMTP id t190mr12606428pgd.227.1508295466934; Tue, 17 Oct 2017 19:57:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508295466; cv=none; d=google.com; s=arc-20160816; b=Doi0MHH9vhfB2CrO+CRH/vWGHJNXfC/pNaiAmvNTwZBAjkeY4n+rCy8AUvuQr22FhA A5aYJe3ER4xS0d8OJdOCcKso/zVG1jf7QjbDbih/NPLNLOt6hnKaDDXF1U+bPFr1d1QO P32gsbg3PT1jJlEl+/BzFUt1dUEWUi/xllK9Zp+RXwuMdfUoAPHHXRnM5FWDGfUsv4QC 2HcqBFiNmeqYLhcSzt7UP3ySYMx7IbeFpOP8nHrN96nXqrhg8cGfaEwOKuXNvvtsT3BH vrgbmNtew/wA0+qMffUXgqOcLkjyNUt+cAJHjQ6XxQa8S0yjam5KcmFiE+LADBcmcsIA Aqhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=GznZbIXvEzeMjpC6sOElqLdfFfRBiAiZGXubHcqzcuY=; b=S9XUxLH4iJNc5ez11LwGt45fwo60fpELYnGUt2KKAmA4nWdndnYgXBIgdArQ1HLSEq CPDQVD1ZkXmAVYxsnjGh/9p57wDj3uh0c/BYnOsW3PQaJdqeHS7WXFjA6upwsL8ubZUk CgX8+QsTopJXB8Yt3EdMVBqZhTUk9HV3/PDFsrwGysJs/2gkP6GwR7js9LU0cuY/tA0A 6G3KvOeK7HMLay89B+eJCEjRpAo2KLICsEgJIDlrAPpKfPuE/KyO/YQE+elEYvdLkbWq 4z4dHBvz9jc0LBvqWMIom1qvdnHK+6QxGimdpafavWClNJbw/iFJ3Wem6FzKYKkHNbG2 TZfA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si577180plm.686.2017.10.17.19.57.46; Tue, 17 Oct 2017 19:57:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757812AbdJRC5p (ORCPT + 27 others); Tue, 17 Oct 2017 22:57:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:8930 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757471AbdJRC5j (ORCPT ); Tue, 17 Oct 2017 22:57:39 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJG66697; Wed, 18 Oct 2017 10:57:24 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:02 +0800 From: Jiancheng Xue To: , CC: , , , , , Jiancheng Xue Subject: [PATCH 0/3] add more clock definitions for hi3798cv200-poplar board Date: Wed, 18 Oct 2017 07:00:26 -0400 Message-ID: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59E6C315.004C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4c92e1801004b13f3eb7dfe3894a768f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add more clock definitions for hi3798cv200-poplar board. Younian Wang (1): clk: hisilicon: correct ir clock rate for hi3798cv200 SoC tianshuliang (2): clk: hisilicon: add hisi phase clock support clk: hisilicon: add emmc sample and drive clock for hi3798cv200 SoC drivers/clk/hisilicon/Makefile | 2 +- drivers/clk/hisilicon/clk-hisi-phase.c | 117 ++++++++++++++++++++++++++++++++ drivers/clk/hisilicon/clk.c | 45 ++++++++++++ drivers/clk/hisilicon/clk.h | 22 ++++++ drivers/clk/hisilicon/crg-hi3798cv200.c | 27 +++++++- 5 files changed, 210 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/hisilicon/clk-hisi-phase.c -- 2.7.4