From patchwork Wed Jun 7 15:20:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 103277 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1797198obh; Wed, 7 Jun 2017 07:53:08 -0700 (PDT) X-Received: by 10.98.85.130 with SMTP id j124mr26721013pfb.196.1496847188496; Wed, 07 Jun 2017 07:53:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496847188; cv=none; d=google.com; s=arc-20160816; b=IjSKwhOyTgNTdydQoyabhV/6JlQlqSv5cHdF07kIB2o3OUWXp/ZZFHLjyiyHZo79N8 Y3E4+t9DhBzX/zJU18efNNwVlW5fsoNu/k249Tfar+RwBzREAmPDwCpXrG7cHu4D8yi/ x07SgqiSchWzW5VqmRhP5a+HeP9PDVVCAWjF37blavJjSW2sRUZSqS9KJ2PKbRnrGb7D Md6LONA3dF0//KoAWNbkPFg7O4iBSNOAD0diF2QVxekbXG98qWsurznX56tPXlU/FyQP vzWkEGjelEXHWMjdeU9oK0lk5qnydG7JanUq4rsRdhiTRySk8jI3MP0gFxH85YF7BW3N bOrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=l4agYf4UKd1MAA1+mwAOAnHNa0u22nKQIMl4Tn81C+E=; b=FF8y3hGHaVGRjILrEvfnHfii7rBgpbL3shD9Sc8iXFl6lcp3FCtRcvtXXJmGF3e4l+ rdedRbOMkqlZoFkNFMbtUfKrTxzuUbEHw2HBII6z569bllQSR9cHvLyUcFnFVVSdU7V0 wK1p2urE7lLNrWLip9743ZdJdSkPgikCRYvRkhNde5t3JOGof4M1dmEN7r5MDntvx60L XHdZn919aQFWQbq8Xsr7DVyxhHsGL1aM+HvpiJatveW2LL53ZwGlPX8FYIT5E5rY34oo hbEVJJcfsU4UdcomZ1aswRCny5xSYGZqstcycoF9sOYEwSbSsxNme3b6ZmNiZXwAiwOD bhUA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q125si1934365pgq.187.2017.06.07.07.53.08; Wed, 07 Jun 2017 07:53:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751873AbdFGOxF (ORCPT + 25 others); Wed, 7 Jun 2017 10:53:05 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7777 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751703AbdFGOwU (ORCPT ); Wed, 7 Jun 2017 10:52:20 -0400 Received: from 172.30.72.57 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.57]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APX46280; Wed, 07 Jun 2017 22:50:50 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Wed, 7 Jun 2017 22:50:43 +0800 From: John Garry To: , CC: , , , , , John Garry Subject: [PATCH v4 00/23] hisi_sas: hip08 support Date: Wed, 7 Jun 2017 23:20:03 +0800 Message-ID: <1496848826-20534-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.593812CB.00C0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fb8e036abd6361b6a4e83a8704624717 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is refactored so it can support both platform and pci device-based controllers. New hw layer file hisi_sas_v3_hw.c is added for v3 hw support, which also includes pci device proving and initialisation. Common functionality is still in hisi_sas_main.c, along with platform device probing and initialization. As for the patches, (ignoring #1-3) the first few reorganise some functions from v2 hw.c into main.c, as they are required for v3 hw. Then support is added for pci device-based controller in subsequent patches. And then hip08 support is added in the final patches. Differences to v3 series: - Addressed Christoph's comments, including: - remove msi disable in probe, and improve irq registration and deregistration - remove hisi_sas_is_rw_cmd() to check underflow, and use scsi_cmnd underflow field instead Differences to v2 series: - Add patch to change hisi_sas_device.device_id size - Add device dq pointer - Remove hisi_sas_v3_hw prototype in v3 driver - Add explicit comment in hisi_sas_get_fw_info() Differences to v1 series: - Addressed Arnd's comments, including: - read sas address from device node DSD under PCI host bridge - add comment in fatal axi error patch commit log regarding controller reset - eliminate hisi_sas_pci_init.c, and move functionality into hisi_sas_v3_hw.c, eliminating one layer of indirection John Garry (5): scsi: hisi_sas: define hisi_sas_device.device_id as int scsi: hisi_sas: add pci_dev in hisi_hba struct scsi: hisi_sas: create hisi_sas_get_fw_info() scsi: hisi_sas: add skeleton v3 hw driver scsi: hisi_sas: add initialisation for v3 pci-based controller Xiang Chen (18): scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() scsi: hisi_sas: optimise the usage of hisi_hba.lock scsi: hisi_sas: relocate get_ata_protocol() scsi: hisi_sas: relocate sata_done_v2_hw() scsi: hisi_sas: relocate get_ncq_tag_v2_hw() scsi: hisi_sas: add v3 hw init scsi: hisi_sas: add v3 hw PHY init scsi: hisi_sas: add phy up/down/bcast and channel ISR scsi: hisi_sas: add v3 cq interrupt handler scsi: hisi_sas: add v3 code to send SSP frame scsi: hisi_sas: add v3 code to send SMP frame scsi: hisi_sas: add v3 code to send ATA frame scsi: hisi_sas: add v3 code for itct setup and free scsi: hisi_sas: add v3 code to send internal abort command scsi: hisi_sas: add get_wideport_bitmap_v3_hw() scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error scsi: hisi_sas: add v3 code to fill some more hw function pointers scsi: hisi_sas: modify internal abort dev flow for v3 hw drivers/scsi/hisi_sas/Kconfig | 10 +- drivers/scsi/hisi_sas/Makefile | 1 + drivers/scsi/hisi_sas/hisi_sas.h | 42 +- drivers/scsi/hisi_sas/hisi_sas_main.c | 355 +++-- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 51 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 179 +-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2265 ++++++++++++++++++++++++++++++++ 7 files changed, 2638 insertions(+), 265 deletions(-) create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c -- 1.9.1