From patchwork Wed May 31 14:32:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 100762 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp339622qge; Wed, 31 May 2017 07:05:30 -0700 (PDT) X-Received: by 10.84.173.195 with SMTP id p61mr89839214plb.83.1496239530281; Wed, 31 May 2017 07:05:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496239530; cv=none; d=google.com; s=arc-20160816; b=CQ9WcLsMgmye+Wp43hukw+lBC87/h9WrZxfzqcmabUrHqT/SYXHpYnZitW7vlSERTX fk+fFvT0SwtA74KPek7QIfAYEppqfeT9us0+9TK2GVILWHm0WdB4i6F35yyH7CM7HUqV r/ecAqbeG0U+GnOP5QJOI1LrLdEwyIWtLIN+u6NRYBJMobHcz9DfAWhqcWRdZ4msFm/v Xa+XsIWLpbFing2UjIiToiG50bn2M80p4ycDgbWIE0Zj5rV0s2c+3YOza0Ybv4TzU7Wr mNr4gK7tIFMqDWYWZonDeGDVlNSrdpHCxoiFp0DA0W6syHOD9m8tkM59dICIYtfGJMJa Uqvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=fuNDE4b+tfLrXw635yplwpjwPvimVxisb0mIAw3pioc=; b=VSS6Y5LKFyGN8bpEA1l8We+NQ+DCDFywFIxihja0OfQZ5FRZz0fpKNPMk+yKP7NLyJ q0en8/6hyyVjA8FAjHT+ggizTryq4wpzTzvYLA09KvACTDNjGR2XLaY13jDpOapnu2sP F5cbqe8QSzmK2mFFwn7WPAf7ircjoHBkZEvkjsAIPEIKQUONbQwzM0Afx3i3h3oqPKqJ B5YMuWcrzxvaTN6gSPvwFHVdm6W8R5NEAfLsJd+rBz1t163afoZ5EVEhs8QaPhb1beh7 bGd5jHCDhBan2A2sYDv0LbOn8B231XqYn+7SeObItWrlll7V/3YRV36pJGP90exixb9b RlFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6si16812852pfe.109.2017.05.31.07.05.29; Wed, 31 May 2017 07:05:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751252AbdEaOFI (ORCPT + 25 others); Wed, 31 May 2017 10:05:08 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6927 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751032AbdEaOFG (ORCPT ); Wed, 31 May 2017 10:05:06 -0400 Received: from 172.30.72.56 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.56]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP17993; Wed, 31 May 2017 22:05:01 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Wed, 31 May 2017 22:04:54 +0800 From: John Garry To: , CC: , , , , , John Garry Subject: [PATCH v3 00/23] hisi_sas: hip08 support Date: Wed, 31 May 2017 22:32:52 +0800 Message-ID: <1496241195-217678-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.592ECD8E.0080, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9078f60814053bd34cde975eb7f0e37b Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is refactored so it can support both platform and pci device-based controllers. New hw layer file hisi_sas_v3_hw.c is added for v3 hw support, which also includes pci device proving and initialisation. Common functionality is still in hisi_sas_main.c, along with platform device probing and initialization. As for the patches, (ignoring #1-3) the first few reorganise some functions from v2 hw.c into main.c, as they are required for v3 hw. Then support is added for pci device-based controller in subsequent patches. And then hip08 support is added in the final patches. Differences to v2 series: - Add patch to change hisi_sas_device.device_id size - Add device dq pointer - Remove hisi_sas_v3_hw prototype in v3 driver - Add explicit comment in hisi_sas_get_fw_info() Differences to v1 series: - Addressed Arnd's comments, including: - read sas address from device node DSD under PCI host bridge - add comment in fatal axi error patch commit log regarding controller reset - eliminate hisi_sas_pci_init.c, and move functionality into hisi_sas_v3_hw.c, eliminating one layer of indirection John Garry (5): scsi: hisi_sas: define hisi_sas_device.device_id as int scsi: hisi_sas: add pci_dev in hisi_hba struct scsi: hisi_sas: create hisi_sas_get_fw_info() scsi: hisi_sas: add skeleton v3 hw driver scsi: hisi_sas: add initialisation for v3 pci-based controller Xiang Chen (18): scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() scsi: hisi_sas: optimise the usage of hisi_hba.lock scsi: hisi_sas: relocate get_ata_protocol() scsi: hisi_sas: relocate sata_done_v2_hw() scsi: hisi_sas: relocate get_ncq_tag_v2_hw() scsi: hisi_sas: add v3 hw init scsi: hisi_sas: add v3 hw PHY init scsi: hisi_sas: add phy up/down/bcast and channel ISR scsi: hisi_sas: add v3 cq interrupt handler scsi: hisi_sas: add v3 code to send SSP frame scsi: hisi_sas: add v3 code to send SMP frame scsi: hisi_sas: add v3 code to send ATA frame scsi: hisi_sas: add v3 code for itct setup and free scsi: hisi_sas: add v3 code to send internal abort command scsi: hisi_sas: add get_wideport_bitmap_v3_hw() scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error scsi: hisi_sas: add v3 code to fill some more hw function pointers scsi: hisi_sas: modify internal abort dev flow for v3 hw drivers/scsi/hisi_sas/Kconfig | 10 +- drivers/scsi/hisi_sas/Makefile | 1 + drivers/scsi/hisi_sas/hisi_sas.h | 37 +- drivers/scsi/hisi_sas/hisi_sas_main.c | 393 ++++-- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 51 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 179 +-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2234 ++++++++++++++++++++++++++++++++ 7 files changed, 2640 insertions(+), 265 deletions(-) create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c -- 1.9.1