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[209.132.180.67]) by mx.google.com with ESMTP id c194si6340542pfc.14.2017.03.17.08.04.45; Fri, 17 Mar 2017 08:04:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751287AbdCQPE3 (ORCPT + 12 others); Fri, 17 Mar 2017 11:04:29 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:35511 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751010AbdCQPEX (ORCPT ); Fri, 17 Mar 2017 11:04:23 -0400 Received: by mail-pg0-f49.google.com with SMTP id b129so42942874pgc.2 for ; Fri, 17 Mar 2017 08:03:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=H+b9NkRxZtUVRw3vWB3ciO2COnf3k1Qbgah2DOP6guQ=; b=LSCHA87qPQLho5jsePf274iCu4aHHGm/EOV2kokZtfqNRgL89+3bH1k/P7ZczHvosU E8dNKzeN2iqPFDx5DTyz3MXZOdFwmM2KWPmz0pk//kF58r1qYcOTd+kV3la6HSHnAwPv MiBCSS519TsLQsM9h2fhZxck/+D3svndaJWd0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=H+b9NkRxZtUVRw3vWB3ciO2COnf3k1Qbgah2DOP6guQ=; b=I3Kfa4K8fnPOBWnVA6GJmQf28dk8i+iuwaDDY9PJRtnIWZYCWf92KfE3lDToL2PCxO YHRLUhLH4z7xW7OrTclc7I7mZK4YXg6m4FvV3ZJN5nI0fWIaL02hU/6mDFbLXi4yTrCw /jWprDBWX7fRy1BYRNuzDO3uUUdhIbx0wIzcX36hVbb5kJriPfwq844U4GB3OH8PxoTJ 4Qq/SBqxzsTh9n7Gsii0yZ+RD9tMcfBeWio5WMAdogBbUnjC3pQDNJ/5YdgBmAsrbZjy 6Fux18s+OKNQLYbpQsvFAGSb5+tytDYJ3srqLOKhe/fOZQmJfuB10AMplsOWWuIUeRwL y67Q== X-Gm-Message-State: AFeK/H3cCTHzQYHs97EGI8ZJgggkLcwlq2AJvjuhxKJbUQSlxjSZSOfDiL0rwBbxeQkdpKk/ X-Received: by 10.84.195.129 with SMTP id j1mr20214536pld.88.1489763016823; Fri, 17 Mar 2017 08:03:36 -0700 (PDT) Received: from localhost.localdomain ([103.230.219.215]) by smtp.gmail.com with ESMTPSA id f125sm17482582pfc.4.2017.03.17.08.03.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 08:03:35 -0700 (PDT) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Leo Yan , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, Suzuki.Poulose@arm.com, sudeep.holla@arm.com Subject: [PATCH v4 0/7] coresight: enable debug module Date: Fri, 17 Mar 2017 23:02:16 +0800 Message-Id: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The Sample-based Profiling Extension" has description for sampling registers, we can utilize these registers to check program counter value with combined CPU exception level, secure state, etc. So this is helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop with IRQ disabled; the 'hang' CPU cannot switch context and handle any interrupt, so it cannot handle SMP call for stack dump, etc. This patch series is to enable coresight debug module with sample-based registers and register call back notifier for PCSR register dumping when panic happens, so we can see below dumping info for panic; and this patch series has considered the conditions for access permission for debug registers self, so this can avoid access debug registers when CPU power domain is off; the driver also try to figure out the CPU is in secure or non-secure state. Patch 0001 is to document the dt binding. Patch 0002 is used to fix the func of_get_coresight_platform_data() doesn't properly drop the reference to the CPU node pointer; and patch 0003 is refactor to add new function of_coresight_get_cpu(). Patch 0004 is the driver for CPU debug module, which is Based on patches 0002/0003. Patches 0005/0006 in this series are to enable debug unit on 96boards Hikey, patch 0005 is to add apb clock for debug unit and patch 0006 is to add DT nodes for debug unit. Patch 0007 is to enable debug on 96boards DB410c. Have verified on both two boards. As result we can get below log after input command: echo c > /proc/sysrq-trigger: ARM external debug module: CPU[0]: EDPRSR: 0000000b (Power:On DLK:Unlock) EDPCSR: [] handle_IPI+0xe4/0x150 EDCIDSR: 00000000 EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) CPU[1]: EDPRSR: 0000000b (Power:On DLK:Unlock) EDPCSR: [] debug_notifier_call+0x108/0x288 EDCIDSR: 00000000 EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) [...] Changes from v3: * Added Suzuki K Poulose's patch to fix issue for the func of_get_coresight_platform_data() doesn't properly drop the reference to the CPU node pointer. * According to Suzuki suggestion, added code to handl the corner case for ARMv8 CPU with aarch32 mode. * According to Suzuki suggestion, changed compatible string to "arm,coresight-cpu-debug". * According to Mathieu suggestion, added "power-domains" as optional properties. Changes from v2: * According to Mathieu Poirier suggestion, applied some minor fixes. * Added two extra patches for enabling debug module on Hikey. Changes from v1: * According to Mike Leach suggestion, removed the binding for debug module clocks which have been directly provided by CPU clocks. * According to Mathieu Poirier suggestion, added function of_coresight_get_cpu() and some minor refactors for debug module driver. Changes from RFC: * According to Mike Leach suggestion, added check for EDPRSR to avoid lockup; added supporting EDVIDSR and EDCIDSR registers. * According to Mark Rutland and Mathieu Poirier suggestion, rewrote the documentation for DT binding. * According to Mark and Mathieu suggestion, refined debug driver. Leo Yan (6): coresight: bindings for CPU debug module coresight: refactor with function of_coresight_get_cpu coresight: add support for CPU debug module clk: hi6220: add debug APB clock arm64: dts: hi6220: register debug module arm64: dts: qcom: msm8916: Add debug unit Suzuki K Poulose (1): coresight: of_get_coresight_platform_data: Add missing of_node_put .../bindings/arm/coresight-cpu-debug.txt | 46 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 ++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 ++ drivers/clk/hisilicon/clk-hi6220.c | 1 + drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 407 +++++++++++++++++++++ drivers/hwtracing/coresight/of_coresight.c | 39 +- include/dt-bindings/clock/hi6220-clock.h | 5 +- include/linux/coresight.h | 2 + 10 files changed, 594 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c -- 2.7.4