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Mon, 19 May 2025 02:43:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEZH8Dj3PuS6Ytm+ZrZel0YOH28lKM6PLPGcCy1a6ugOdm4Fbbt13k3NmX+lfNghb6SE7j+aA== X-Received: by 2002:a05:6a20:a108:b0:1f5:882e:60f with SMTP id adf61e73a8af0-216218c6475mr16209456637.17.1747647787108; Mon, 19 May 2025 02:43:07 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-742a97398f8sm5809092b3a.78.2025.05.19.02.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 02:43:06 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Mon, 19 May 2025 15:12:19 +0530 Subject: [PATCH v3 06/11] PCI: qcom: Add support for PCIe bus bw scaling Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250519-mhi_bw_up-v3-6-3acd4a17bbb5@oss.qualcomm.com> References: <20250519-mhi_bw_up-v3-0-3acd4a17bbb5@oss.qualcomm.com> In-Reply-To: <20250519-mhi_bw_up-v3-0-3acd4a17bbb5@oss.qualcomm.com> To: Bjorn Helgaas , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Johannes Berg , Jeff Johnson , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru , Jeff Johnson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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So as part of pre_bw_scale() disable ASPM and as part of post_scale_bus_bw() enable ASPM back. As the driver needs to enable the ASPM states that are enabled by the system, save PCI ASPM states before disabling them and in post_scale_bus_bw() use the saved ASPM states to enable back the ASPM. Update ICC & OPP votes based on the requested speed so that RPMh votes get updated based on the speed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index bd984cde8d3bd688b2ac32566b0e9cdbc70905c0..491324d44785535b84460d468727b8c356ca1040 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -276,10 +276,16 @@ struct qcom_pcie { struct dentry *debugfs; bool suspended; bool use_pm_opp; + int aspm_state; /* Store ASPM state used in pre & post scale bus bw */ }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int current_speed); +static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int current_speed); + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -1263,6 +1269,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_assert_reset; } + pp->bridge->pre_scale_bus_bw = qcom_pcie_host_pre_scale_bus_bw; + pp->bridge->post_scale_bus_bw = qcom_pcie_host_post_scale_bus_bw; return 0; err_assert_reset: @@ -1328,6 +1336,61 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width) return ret; } +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u32 offset, status, width; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + return qcom_pcie_set_icc_opp(pcie, speed, width); +} + +static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int current_speed) +{ + struct dw_pcie_rp *pp = bridge->bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + struct pci_dev *child; + + /* Get function 0 of downstream device */ + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) + if (PCI_FUNC(child->devfn) == 0) + break; + + pci_enable_link_state_locked(child, pcie->aspm_state); + + qcom_pcie_scale_bw(pp, current_speed); +} + +static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int target_speed) +{ + struct dw_pcie_rp *pp = bridge->bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + struct pci_dev *child; + + /* Get function 0 of downstream device */ + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) + if (PCI_FUNC(child->devfn) == 0) + break; + /* + * QCOM controllers doesn't support link re-train with ASPM enabled. + * Disable ASPM as part of pre_bus_bw() and enable them back as + * part of post_bus_bw(). + */ + pcie->aspm_state = pcie_aspm_enabled(child); + pci_disable_link_state_locked(child, PCIE_LINK_STATE_ALL); + + return qcom_pcie_scale_bw(pp, target_speed); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .init = qcom_pcie_host_init, .deinit = qcom_pcie_host_deinit,