@@ -3376,6 +3376,12 @@ struct rtw89_reg5_def {
u32 data;
};
+struct rtw89_reg_imr {
+ u32 addr;
+ u32 clr;
+ u32 set;
+};
+
struct rtw89_phy_table {
const struct rtw89_reg2_def *regs;
u32 n_regs;
@@ -3585,6 +3591,11 @@ struct rtw89_imr_info {
u32 tmac_imr_set;
};
+struct rtw89_imr_table {
+ const struct rtw89_reg_imr *regs;
+ u32 n_regs;
+};
+
struct rtw89_xtal_info {
u32 xcap_reg;
u32 sc_xo_mask;
@@ -3779,6 +3790,8 @@ struct rtw89_chip_info {
const struct rtw89_reg_def *dcfo_comp;
u8 dcfo_comp_sft;
const struct rtw89_imr_info *imr_info;
+ const struct rtw89_imr_table *imr_dmac_table;
+ const struct rtw89_imr_table *imr_cmac_table;
const struct rtw89_rrsr_cfgs *rrsr_cfgs;
struct rtw89_reg_def bss_clr_vld;
u32 bss_clr_map_reg;
@@ -3740,6 +3740,39 @@
#define B_BE_DIS_CLK_REG1_GATE BIT(1)
#define B_BE_DIS_CLK_REG0_GATE BIT(0)
+#define R_BE_AFE_CTRL1 0x0024
+#define B_BE_R_SYM_WLCMAC0_P4_PC_EN BIT(28)
+#define B_BE_R_SYM_WLCMAC0_P3_PC_EN BIT(27)
+#define B_BE_R_SYM_WLCMAC0_P2_PC_EN BIT(26)
+#define B_BE_R_SYM_WLCMAC0_P1_PC_EN BIT(25)
+#define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24)
+#define B_BE_DATAMEM_PC3_EN BIT(23)
+#define B_BE_DATAMEM_PC2_EN BIT(22)
+#define B_BE_DATAMEM_PC1_EN BIT(21)
+#define B_BE_DATAMEM_PC_EN BIT(20)
+#define B_BE_DMEM7_PC_EN BIT(19)
+#define B_BE_DMEM6_PC_EN BIT(18)
+#define B_BE_DMEM5_PC_EN BIT(17)
+#define B_BE_DMEM4_PC_EN BIT(16)
+#define B_BE_DMEM3_PC_EN BIT(15)
+#define B_BE_DMEM2_PC_EN BIT(14)
+#define B_BE_DMEM1_PC_EN BIT(13)
+#define B_BE_IMEM4_PC_EN BIT(12)
+#define B_BE_IMEM3_PC_EN BIT(11)
+#define B_BE_IMEM2_PC_EN BIT(10)
+#define B_BE_IMEM1_PC_EN BIT(9)
+#define B_BE_IMEM0_PC_EN BIT(8)
+#define B_BE_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
+#define B_BE_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
+#define B_BE_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
+#define B_BE_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
+#define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0)
+#define B_BE_AFE_CTRL1_SET (B_BE_R_SYM_WLCMAC1_PC_EN | \
+ B_BE_R_SYM_WLCMAC1_P1_PC_EN | \
+ B_BE_R_SYM_WLCMAC1_P2_PC_EN | \
+ B_BE_R_SYM_WLCMAC1_P3_PC_EN | \
+ B_BE_R_SYM_WLCMAC1_P4_PC_EN)
+
#define R_BE_EFUSE_CTRL 0x0030
#define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
#define B_BE_EF_RDY BIT(29)
@@ -3827,6 +3860,30 @@
#define B_BE_PCI_CKRDY_OPT BIT(1)
#define B_BE_PCI_VAUX_EN BIT(0)
+#define R_BE_SYS_ISO_CTRL_EXTEND 0x0080
+#define B_BE_R_SYM_ISO_DMEM62PP BIT(29)
+#define B_BE_R_SYM_ISO_DMEM52PP BIT(28)
+#define B_BE_R_SYM_ISO_DMEM42PP BIT(27)
+#define B_BE_R_SYM_ISO_DMEM32PP BIT(26)
+#define B_BE_R_SYM_ISO_DMEM22PP BIT(25)
+#define B_BE_R_SYM_ISO_DMEM12PP BIT(24)
+#define B_BE_R_SYM_ISO_IMEM42PP BIT(22)
+#define B_BE_R_SYM_ISO_IMEM32PP BIT(21)
+#define B_BE_R_SYM_ISO_IMEM22PP BIT(20)
+#define B_BE_R_SYM_ISO_IMEM12PP BIT(19)
+#define B_BE_R_SYM_ISO_IMEM02PP BIT(18)
+#define B_BE_R_SYM_ISO_AON_OFF2PP BIT(15)
+#define B_BE_R_SYM_PWC_HCILA BIT(13)
+#define B_BE_R_SYM_PWC_PD12V BIT(12)
+#define B_BE_R_SYM_PWC_UD12V BIT(11)
+#define B_BE_R_SYM_PWC_BTBRG BIT(10)
+#define B_BE_R_SYM_LDOBTSDIO_EN BIT(9)
+#define B_BE_R_SYM_LDOSPDIO_EN BIT(8)
+#define B_BE_R_SYM_ISO_HCILA BIT(4)
+#define B_BE_R_SYM_ISO_BTBRG2PP BIT(2)
+#define B_BE_R_SYM_ISO_BTSDIO2PP BIT(1)
+#define B_BE_R_SYM_ISO_SPDIO2PP BIT(0)
+
#define R_BE_PLATFORM_ENABLE 0x0088
#define B_BE_HOLD_AFTER_RESET BIT(11)
#define B_BE_SYM_WLPLT_MEM_MUX_EN BIT(10)
@@ -3869,6 +3926,18 @@
#define B_BE_SYSON_DIS_PMCR_BE_WRMSK BIT(2)
#define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)
+#define R_BE_PCIE_MIO_INTF 0x00E4
+#define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24)
+#define B_BE_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
+#define B_BE_PCIE_MIO_ASIF BIT(15)
+#define B_BE_PCIE_MIO_BYIOREG BIT(13)
+#define B_BE_PCIE_MIO_RE BIT(12)
+#define B_BE_PCIE_MIO_WE_MASK GENMASK(11, 8)
+#define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
+
+#define R_BE_PCIE_MIO_INTD 0x00E8
+#define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
+
#define R_BE_HALT_H2C_CTRL 0x0160
#define B_BE_HALT_H2C_TRIGGER BIT(0)
@@ -4034,6 +4103,25 @@
#define B_BE_DCPU_EN BIT(1)
#define B_BE_DCPU_PLATFORM_EN BIT(0)
+#define R_BE_PL_AXIDMA_IDCT_MSK 0x0910
+#define B_BE_PL_AXIDMA_RRESP_ERR_MASK BIT(6)
+#define B_BE_PL_AXIDMA_BRESP_ERR_MASK BIT(5)
+#define B_BE_PL_AXIDMA_FC_ERR_MASK BIT(4)
+#define B_BE_PL_AXIDMA_TXBD_LEN0_MASK BIT(3)
+#define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR_MASK BIT(2)
+#define B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK BIT(1)
+#define B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK BIT(0)
+#define B_BE_PL_AXIDMA_IDCT_MSK_CLR (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
+ B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
+ B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
+ B_BE_PL_AXIDMA_FC_ERR_MASK | \
+ B_BE_PL_AXIDMA_BRESP_ERR_MASK | \
+ B_BE_PL_AXIDMA_RRESP_ERR_MASK)
+#define B_BE_PL_AXIDMA_IDCT_MSK_SET (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
+ B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
+ B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
+ B_BE_PL_AXIDMA_FC_ERR_MASK)
+
#define R_BE_FILTER_MODEL_ADDR 0x0C04
#define R_BE_WLAN_WDT 0x3050
@@ -4247,11 +4335,316 @@
#define B_BE_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
#define B_BE_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
+#define R_BE_DISP_OTHER_IMR 0x8870
+#define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31)
+#define B_BE_REUSE_EN_ERR_INT_EN BIT(30)
+#define B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
+#define B_BE_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
+#define B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
+#define B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
+#define B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
+#define B_BE_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
+#define B_BE_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
+#define B_BE_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
+#define B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
+#define B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
+#define B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
+#define B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
+#define B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
+#define B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
+#define B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
+#define B_BE_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
+#define B_BE_PLE_OUTPUT_ERR_INT_EN BIT(12)
+#define B_BE_PLE_RESPOSE_ERR_INT_EN BIT(11)
+#define B_BE_PLE_BURST_NUM_ERR_INT_EN BIT(10)
+#define B_BE_PLE_NULL_PKT_ERR_INT_EN BIT(9)
+#define B_BE_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
+#define B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
+#define B_BE_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
+#define B_BE_WDE_OUTPUT_ERR_INT_EN BIT(4)
+#define B_BE_WDE_RESPONSE_ERR_INT_EN BIT(3)
+#define B_BE_WDE_BURST_NUM_ERR_INT_EN BIT(2)
+#define B_BE_WDE_NULL_PKT_ERR_INT_EN BIT(1)
+#define B_BE_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
+#define B_BE_DISP_OTHER_IMR_CLR (B_BE_WDE_FLOW_CTRL_ERR_INT_EN | \
+ B_BE_WDE_NULL_PKT_ERR_INT_EN | \
+ B_BE_WDE_BURST_NUM_ERR_INT_EN | \
+ B_BE_WDE_RESPONSE_ERR_INT_EN | \
+ B_BE_WDE_OUTPUT_ERR_INT_EN | \
+ B_BE_HDR_RX_TIMEOUT_ERR_INT_EN | \
+ B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN | \
+ B_BE_PLE_FLOW_CTRL_ERR_INT_EN | \
+ B_BE_PLE_NULL_PKT_ERR_INT_EN | \
+ B_BE_PLE_BURST_NUM_ERR_INT_EN | \
+ B_BE_PLE_RESPOSE_ERR_INT_EN | \
+ B_BE_PLE_OUTPUT_ERR_INT_EN | \
+ B_BE_CDR_RX_TIMEOUT_ERR_INT_EN | \
+ B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN | \
+ B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
+ B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
+ B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN | \
+ B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN | \
+ B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN | \
+ B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN | \
+ B_BE_REUSE_PKT_CNT_ERR_INT_EN | \
+ B_BE_REUSE_SIZE_ZERO_ERR_INT_EN | \
+ B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN | \
+ B_BE_REUSE_EN_ERR_INT_EN | \
+ B_BE_REUSE_SIZE_ERR_INT_EN)
+#define B_BE_DISP_OTHER_IMR_SET (B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
+ B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN)
+
+#define R_BE_DISP_HOST_IMR 0x8874
+#define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
+#define B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
+#define B_BE_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
+#define B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
+#define B_BE_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
+#define B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
+#define B_BE_HR_SHIFT_EN_ERR_INT_EN BIT(25)
+#define B_BE_HR_AGG_CFG_ERR_INT_EN BIT(24)
+#define B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
+#define B_BE_HT_ILL_CH_ERR_INT_EN BIT(20)
+#define B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
+#define B_BE_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
+#define B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
+#define B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
+#define B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
+#define B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
+#define B_BE_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
+#define B_BE_HT_NON_IDLE_PKT_STR_ERR_EN BIT(11)
+#define B_BE_HT_PRE_SUB_ERR_INT_EN BIT(10)
+#define B_BE_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
+#define B_BE_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
+#define B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
+#define B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
+#define B_BE_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
+#define B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
+#define B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
+#define B_BE_HT_PKT_FAIL_ERR_INT_EN BIT(2)
+#define B_BE_HT_CH_ID_ERR_INT_EN BIT(1)
+#define B_BE_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
+#define B_BE_DISP_HOST_IMR_CLR (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
+ B_BE_HT_CH_ID_ERR_INT_EN | \
+ B_BE_HT_PKT_FAIL_ERR_INT_EN | \
+ B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
+ B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
+ B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN | \
+ B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
+ B_BE_HT_WD_CHKSUM_ERR_INT_EN | \
+ B_BE_HT_PRE_SUB_ERR_INT_EN | \
+ B_BE_HT_NON_IDLE_PKT_STR_ERR_EN | \
+ B_BE_HT_CHKSUM_FSM_ERR_INT_EN | \
+ B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
+ B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN | \
+ B_BE_HT_ILL_CH_ERR_INT_EN | \
+ B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN | \
+ B_BE_HR_AGG_CFG_ERR_INT_EN | \
+ B_BE_HR_SHIFT_EN_ERR_INT_EN | \
+ B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
+ B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
+ B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
+ B_BE_HR_CHKSUM_FSM_ERR_INT_EN | \
+ B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
+#define B_BE_DISP_HOST_IMR_SET (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
+ B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
+ B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
+ B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
+ B_BE_HT_PRE_SUB_ERR_INT_EN | \
+ B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
+ B_BE_HT_ILL_CH_ERR_INT_EN | \
+ B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
+ B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
+ B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
+
+#define R_BE_DISP_CPU_IMR 0x8878
+#define B_BE_CR_PLD_LEN_ERR_INT_EN BIT(30)
+#define B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
+#define B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
+#define B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
+#define B_BE_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
+#define B_BE_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
+#define B_BE_CR_SHIFT_EN_ERR_INT_EN BIT(24)
+#define B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
+#define B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
+#define B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
+#define B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
+#define B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
+#define B_BE_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
+#define B_BE_CT_F2P_SEQ_ERR_INT_EN BIT(15)
+#define B_BE_CT_F2P_QSEL_ERR_INT_EN BIT(14)
+#define B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
+#define B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
+#define B_BE_CT_PRE_SUB_ERR_INT_EN BIT(11)
+#define B_BE_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
+#define B_BE_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
+#define B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
+#define B_BE_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
+#define B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
+#define B_BE_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
+#define B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
+#define B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
+#define B_BE_CT_CH_ID_ERR_INT_EN BIT(2)
+#define B_BE_CT_PKT_FAIL_ERR_INT_EN BIT(1)
+#define B_BE_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
+#define B_BE_DISP_CPU_IMR_CLR (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
+ B_BE_CT_CH_ID_ERR_INT_EN | \
+ B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
+ B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
+ B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
+ B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN | \
+ B_BE_CT_CHANNEL_DMA_ERR_INT_EN | \
+ B_BE_CT_WD_CHKSUM_ERR_INT_EN | \
+ B_BE_CT_PRE_SUB_ERR_INT_EN | \
+ B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_CT_F2P_QSEL_ERR_INT_EN | \
+ B_BE_CT_F2P_SEQ_ERR_INT_EN | \
+ B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
+ B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
+ B_BE_CR_SHIFT_EN_ERR_INT_EN | \
+ B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
+ B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
+ B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_CR_PLD_LEN_ERR_INT_EN)
+#define B_BE_DISP_CPU_IMR_SET (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
+ B_BE_CT_CH_ID_ERR_INT_EN | \
+ B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
+ B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
+ B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
+ B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
+ B_BE_CT_PRE_SUB_ERR_INT_EN | \
+ B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
+ B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
+ B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
+ B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
+ B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
+ B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
+ B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN)
+
#define R_BE_WDE_PKTBUF_CFG 0x8C08
#define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
#define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8)
#define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)
+#define R_BE_WDE_ERR_IMR 0x8C38
+#define B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
+#define B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
+#define B_BE_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
+#define B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
+#define B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
+#define B_BE_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
+#define B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
+#define B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
+#define B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
+#define B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
+#define B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
+#define B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
+#define B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
+#define B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
+#define B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
+#define B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
+#define B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
+#define B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
+#define B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
+#define B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
+#define B_BE_WDE_GETNPG_STRPG_ERR_INT_EN BIT(7)
+#define B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
+#define B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
+#define B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
+#define B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
+#define B_BE_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
+#define B_BE_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
+#define B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
+#define B_BE_WDE_ERR_IMR_CLR (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
+ B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
+ B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
+ B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
+ B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
+ B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
+ B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
+ B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
+ B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
+ B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
+ B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
+ B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
+ B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
+ B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
+ B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
+ B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
+#define B_BE_WDE_ERR_IMR_SET (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
+ B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
+ B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
+ B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
+ B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
+ B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
+ B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
+ B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
+ B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
+ B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
+ B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
+ B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
+ B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
+ B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
+ B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
+ B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
+ B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
+ B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
+
#define R_BE_WDE_QTA0_CFG 0x8C40
#define B_BE_WDE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
#define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
@@ -4272,11 +4665,102 @@
#define B_BE_WDE_Q4_MAX_SIZE_MASK GENMASK(27, 16)
#define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
+#define R_BE_WDE_ERR1_IMR 0x8CC0
+#define B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN BIT(8)
+#define B_BE_WDE_ERR1_IMR_CLR B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
+#define B_BE_WDE_ERR1_IMR_SET B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
+
#define R_BE_PLE_PKTBUF_CFG 0x9008
#define B_BE_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
#define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8)
#define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)
+#define R_BE_PLE_ERR_IMR 0x9038
+#define B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
+#define B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
+#define B_BE_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
+#define B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
+#define B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
+#define B_BE_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
+#define B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
+#define B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
+#define B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
+#define B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
+#define B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
+#define B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
+#define B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
+#define B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
+#define B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
+#define B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
+#define B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
+#define B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
+#define B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
+#define B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
+#define B_BE_PLE_GETNPG_STRPG_ERR_INT_EN BIT(7)
+#define B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
+#define B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
+#define B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
+#define B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
+#define B_BE_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
+#define B_BE_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
+#define B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
+#define B_BE_PLE_ERR_IMR_CLR (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
+ B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
+ B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
+ B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
+ B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
+ B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
+ B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
+ B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
+ B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
+ B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
+ B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
+ B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
+ B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
+ B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
+ B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
+ B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
+#define B_BE_PLE_ERR_IMR_SET (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
+ B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
+ B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
+ B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
+ B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
+ B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
+ B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
+ B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
+ B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
+ B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
+ B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
+ B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
+ B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
+ B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
+ B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
+ B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
+ B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
+ B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
+
#define R_BE_PLE_QTA0_CFG 0x9040
#define B_BE_PLE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
#define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
@@ -4329,6 +4813,17 @@
#define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16)
#define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)
+#define R_BE_PLE_ERRFLAG1_IMR 0x90C0
+#define B_BE_PLE_SRCHPG_PGOFST_IMR BIT(26)
+#define B_BE_PLE_SRCHPG_STRPG_IMR BIT(25)
+#define B_BE_PLE_SRCHPG_FRZTO_IMR BIT(24)
+#define B_BE_PLE_ERRFLAG1_IMR_CLR (B_BE_PLE_SRCHPG_FRZTO_IMR | \
+ B_BE_PLE_SRCHPG_STRPG_IMR | \
+ B_BE_PLE_SRCHPG_PGOFST_IMR)
+#define B_BE_PLE_ERRFLAG1_IMR_SET (B_BE_PLE_SRCHPG_FRZTO_IMR | \
+ B_BE_PLE_SRCHPG_STRPG_IMR | \
+ B_BE_PLE_SRCHPG_PGOFST_IMR)
+
#define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110
#define B_BE_PLE_DFI_ACTIVE BIT(31)
#define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
@@ -4337,6 +4832,100 @@
#define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114
#define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
+#define R_BE_WDRLS_CFG 0x9408
+#define B_BE_WDRLS_DIS_AGAC BIT(31)
+#define B_BE_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
+#define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6)
+#define B_BE_WDRLS_MODE_MASK GENMASK(1, 0)
+
+#define R_BE_WDRLS_ERR_IMR 0x9430
+#define B_BE_WDRLS_RPT3_FRZTO_ERR_INT_EN BIT(21)
+#define B_BE_WDRLS_RPT3_AGGNUM0_ERR_INT_EN BIT(20)
+#define B_BE_WDRLS_RPT2_FRZTO_ERR_INT_EN BIT(17)
+#define B_BE_WDRLS_RPT2_AGGNUM0_ERR_INT_EN BIT(16)
+#define B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
+#define B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
+#define B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
+#define B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
+#define B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
+#define B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
+#define B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
+#define B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
+#define B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
+#define B_BE_WDRLS_ERR_IMR_CLR (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
+ B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
+ B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
+ B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
+ B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
+ B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
+#define B_BE_WDRLS_ERR_IMR_SET (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
+ B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
+ B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
+ B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
+ B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
+ B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
+
+#define R_BE_RLSRPT0_CFG1 0x9444
+#define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
+#define S_BE_WDRLS_FLTR_TXOK 1
+#define S_BE_WDRLS_FLTR_RTYLMT 2
+#define S_BE_WDRLS_FLTR_LIFTIM 4
+#define S_BE_WDRLS_FLTR_MACID 8
+#define B_BE_RLSRPT0_TO_MASK GENMASK(23, 16)
+#define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
+
+#define R_BE_BBRPT_COM_ERR_IMR 0x9608
+#define B_BE_BBRPT_COM_EVT01_ISR_EN BIT(1)
+#define B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN BIT(0)
+#define B_BE_BBRPT_COM_ERR_IMR_CLR (B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN | \
+ B_BE_BBRPT_COM_EVT01_ISR_EN)
+#define B_BE_BBRPT_COM_ERR_IMR_SET B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN
+
+#define R_BE_BBRPT_CHINFO_ERR_IMR 0x9628
+#define B_BE_ERR_BB_ONETEN_INT_EN BIT(1)
+#define B_BE_ERR_GEN_FRZTO_INT_EN BIT(0)
+#define B_BE_BBRPT_CHINFO_ERR_IMR_CLR (B_BE_ERR_GEN_FRZTO_INT_EN | \
+ B_BE_ERR_BB_ONETEN_INT_EN)
+#define B_BE_BBRPT_CHINFO_ERR_IMR_SET (B_BE_ERR_GEN_FRZTO_INT_EN | \
+ B_BE_ERR_BB_ONETEN_INT_EN)
+
+#define R_BE_BBRPT_DFS_ERR_IMR 0x9638
+#define B_BE_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
+#define B_BE_BBRPT_DFS_ERR_IMR_CLR B_BE_BBRPT_DFS_TO_ERR_INT_EN
+#define B_BE_BBRPT_DFS_ERR_IMR_SET B_BE_BBRPT_DFS_TO_ERR_INT_EN
+
+#define R_BE_LA_ERRFLAG_IMR 0x9668
+#define B_BE_LA_IMR_DATA_LOSS BIT(0)
+#define B_BE_LA_ERRFLAG_IMR_CLR B_BE_LA_IMR_DATA_LOSS
+#define B_BE_LA_ERRFLAG_IMR_SET B_BE_LA_IMR_DATA_LOSS
+
+#define R_BE_CH_INFO_DBGFLAG_IMR 0x9688
+#define B_BE_BCHN_EVT01_ISR_EN BIT(29)
+#define B_BE_BCHN_REQTO_ISR_EN BIT(28)
+#define B_BE_CHIF_RXDATA_AFACT_ISR_EN BIT(11)
+#define B_BE_CHIF_RXDATA_BFACT_ISR_EN BIT(10)
+#define B_BE_CHIF_HDR_SEGLEN_ISR_EN BIT(9)
+#define B_BE_CHIF_HDR_INVLD_ISR_EN BIT(8)
+#define B_BE_CHIF_BBONL_BFACT_ISR_EN BIT(4)
+#define B_BE_CHIF_RPT_OVF_ISR_EN BIT(3)
+#define B_BE_DBG_CHIF_DATA_LOSS_ISR_EN BIT(2)
+#define B_BE_CHIF_DATA_WTOUT_ISR_EN BIT(1)
+#define B_BE_CHIF_RPT_WTOUT_ISR_EN BIT(0)
+#define B_BE_CH_INFO_DBGFLAG_IMR_CLR (B_BE_CHIF_RPT_WTOUT_ISR_EN | \
+ B_BE_CHIF_DATA_WTOUT_ISR_EN | \
+ B_BE_DBG_CHIF_DATA_LOSS_ISR_EN | \
+ B_BE_CHIF_RPT_OVF_ISR_EN | \
+ B_BE_CHIF_HDR_INVLD_ISR_EN | \
+ B_BE_CHIF_HDR_SEGLEN_ISR_EN | \
+ B_BE_CHIF_RXDATA_BFACT_ISR_EN | \
+ B_BE_CHIF_RXDATA_AFACT_ISR_EN)
+#define B_BE_CH_INFO_DBGFLAG_IMR_SET 0
+
#define R_BE_WD_BUF_REQ 0x9800
#define B_BE_WD_BUF_REQ_EXEC BIT(31)
#define B_BE_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
@@ -4403,6 +4992,144 @@
#define B_BE_PL_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)
#define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
+#define R_BE_CPUIO_ERR_IMR 0x9888
+#define B_BE_PLEQUE_OP_ERR_INT_EN BIT(12)
+#define B_BE_PLEBUF_OP_ERR_INT_EN BIT(8)
+#define B_BE_WDEQUE_OP_ERR_INT_EN BIT(4)
+#define B_BE_WDEBUF_OP_ERR_INT_EN BIT(0)
+#define B_BE_CPUIO_ERR_IMR_CLR (B_BE_WDEBUF_OP_ERR_INT_EN | \
+ B_BE_WDEQUE_OP_ERR_INT_EN | \
+ B_BE_PLEBUF_OP_ERR_INT_EN | \
+ B_BE_PLEQUE_OP_ERR_INT_EN)
+#define B_BE_CPUIO_ERR_IMR_SET (B_BE_WDEBUF_OP_ERR_INT_EN | \
+ B_BE_WDEQUE_OP_ERR_INT_EN | \
+ B_BE_PLEBUF_OP_ERR_INT_EN | \
+ B_BE_PLEQUE_OP_ERR_INT_EN)
+
+#define R_BE_PKTIN_ERR_IMR 0x9A20
+#define B_BE_SW_MERGE_ERR_INT_EN BIT(1)
+#define B_BE_GET_NULL_PKTID_ERR_INT_EN BIT(0)
+#define B_BE_PKTIN_ERR_IMR_CLR (B_BE_SW_MERGE_ERR_INT_EN | \
+ B_BE_GET_NULL_PKTID_ERR_INT_EN)
+#define B_BE_PKTIN_ERR_IMR_SET (B_BE_SW_MERGE_ERR_INT_EN | \
+ B_BE_GET_NULL_PKTID_ERR_INT_EN)
+
+#define R_BE_MPDU_TX_ERR_IMR 0x9BF4
+#define B_BE_TX_TIMEOUT_ERR_EN BIT(0)
+#define B_BE_MPDU_TX_ERR_IMR_CLR B_BE_TX_TIMEOUT_ERR_EN
+#define B_BE_MPDU_TX_ERR_IMR_SET 0
+
+#define R_BE_MPDU_RX_ERR_IMR 0x9CF4
+#define B_BE_LEN_ERR_IMR BIT(3)
+#define B_BE_TIMEOUT_ERR_IMR BIT(1)
+#define B_BE_MPDU_RX_ERR_IMR_CLR B_BE_TIMEOUT_ERR_IMR
+#define B_BE_MPDU_RX_ERR_IMR_SET 0
+
+#define R_BE_SEC_ERROR_IMR 0x9D2C
+#define B_BE_QUEUE_OPERATION_HANG_IMR BIT(4)
+#define B_BE_SEC1_RX_HANG_IMR BIT(3)
+#define B_BE_SEC1_TX_HANG_IMR BIT(2)
+#define B_BE_RX_HANG_IMR BIT(1)
+#define B_BE_TX_HANG_IMR BIT(0)
+#define B_BE_SEC_ERROR_IMR_CLR (B_BE_TX_HANG_IMR | \
+ B_BE_RX_HANG_IMR | \
+ B_BE_SEC1_TX_HANG_IMR | \
+ B_BE_SEC1_RX_HANG_IMR | \
+ B_BE_QUEUE_OPERATION_HANG_IMR)
+#define B_BE_SEC_ERROR_IMR_SET (B_BE_TX_HANG_IMR | \
+ B_BE_RX_HANG_IMR | \
+ B_BE_SEC1_TX_HANG_IMR | \
+ B_BE_SEC1_RX_HANG_IMR | \
+ B_BE_QUEUE_OPERATION_HANG_IMR)
+
+#define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
+#define B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
+#define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
+#define B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
+#define B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
+#define B_BE_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
+#define B_BE_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
+#define B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
+#define B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
+#define B_BE_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
+#define B_BE_B0_IMR_ERR_USRCTL_REINIT BIT(0)
+#define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
+ B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
+ B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD | \
+ B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN | \
+ B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
+ B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
+ B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
+ B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
+ B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
+ B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
+#define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
+ B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
+ B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
+ B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
+ B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
+ B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
+ B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
+ B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
+
+#define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
+#define B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
+#define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
+#define B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
+#define B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
+#define B_BE_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
+#define B_BE_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
+#define B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
+#define B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
+#define B_BE_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
+#define B_BE_B1_IMR_ERR_USRCTL_REINIT BIT(0)
+#define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
+ B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
+ B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD | \
+ B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN | \
+ B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
+ B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
+ B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
+ B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
+ B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
+ B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
+#define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
+ B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
+ B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
+ B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
+ B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
+ B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
+ B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
+ B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
+
+#define R_BE_MLO_ERR_IDCT_IMR 0xA128
+#define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31)
+#define B_BE_MLO_ERR_IDCT_IMR_1 BIT(30)
+#define B_BE_MLO_ERR_IDCT_IMR_2 BIT(29)
+#define B_BE_MLO_ERR_IDCT_IMR_3 BIT(28)
+#define B_BE_MLO_ERR_IDCT_IMR_CLR (B_BE_MLO_ERR_IDCT_IMR_2 | \
+ B_BE_MLO_ERR_IDCT_IMR_1 | \
+ B_BE_MLO_ERR_IDCT_IMR_0)
+#define B_BE_MLO_ERR_IDCT_IMR_SET (B_BE_MLO_ERR_IDCT_IMR_2 | \
+ B_BE_MLO_ERR_IDCT_IMR_1 | \
+ B_BE_MLO_ERR_IDCT_IMR_0)
+
+#define R_BE_PLRLS_ERR_IMR 0xA218
+#define B_BE_PLRLS_CTL_FRZTO_IMR BIT(0)
+#define B_BE_PLRLS_ERR_IMR_CLR B_BE_PLRLS_CTL_FRZTO_IMR
+#define B_BE_PLRLS_ERR_IMR_SET B_BE_PLRLS_CTL_FRZTO_IMR
+
+#define R_BE_INTERRUPT_MASK_REG 0xA3F0
+#define B_BE_PLE_B_PKTID_ERR_IMR BIT(2)
+#define B_BE_RPT_TIMEOUT_IMR BIT(1)
+#define B_BE_SEARCH_TIMEOUT_IMR BIT(0)
+#define B_BE_INTERRUPT_MASK_REG_CLR (B_BE_SEARCH_TIMEOUT_IMR | \
+ B_BE_RPT_TIMEOUT_IMR | \
+ B_BE_PLE_B_PKTID_ERR_IMR)
+#define B_BE_INTERRUPT_MASK_REG_SET (B_BE_SEARCH_TIMEOUT_IMR | \
+ B_BE_RPT_TIMEOUT_IMR | \
+ B_BE_PLE_B_PKTID_ERR_IMR)
+
#define R_BE_HAXI_INIT_CFG1 0xB000
#define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
#define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24)
@@ -4443,6 +5170,30 @@
#define B_BE_STOP_CH1 BIT(1)
#define B_BE_STOP_CH0 BIT(0)
+#define R_BE_HAXI_IDCT_MSK 0xB0B8
+#define B_BE_HAXI_RRESP_ERR_IDCT_MSK BIT(7)
+#define B_BE_HAXI_BRESP_ERR_IDCT_MSK BIT(6)
+#define B_BE_RXDMA_ERR_FLAG_IDCT_MSK BIT(5)
+#define B_BE_SET_FC_ERROR_FLAG_IDCT_MSK BIT(4)
+#define B_BE_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
+#define B_BE_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
+#define B_BE_RXMDA_STUCK_IDCT_MSK BIT(1)
+#define B_BE_TXMDA_STUCK_IDCT_MSK BIT(0)
+#define B_BE_HAXI_IDCT_MSK_CLR (B_BE_TXMDA_STUCK_IDCT_MSK | \
+ B_BE_RXMDA_STUCK_IDCT_MSK | \
+ B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
+ B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
+ B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
+ B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
+ B_BE_HAXI_RRESP_ERR_IDCT_MSK)
+#define B_BE_HAXI_IDCT_MSK_SET (B_BE_TXMDA_STUCK_IDCT_MSK | \
+ B_BE_RXMDA_STUCK_IDCT_MSK | \
+ B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
+ B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
+ B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
+ B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
+ B_BE_HAXI_RRESP_ERR_IDCT_MSK)
+
#define R_BE_HCI_FC_CTRL 0xB700
#define B_BE_WD_PAGE_MODE_MASK GENMASK(17, 16)
#define B_BE_HCI_FC_CH14_FULL_COND_MASK GENMASK(15, 14)
@@ -4539,6 +5290,12 @@
#define B_BE_SET_MUEDCATIMER_TF_0 BIT(4)
#define B_BE_MUEDCA_EN_0 BIT(0)
+#define R_BE_SCHEDULE_ERR_IMR 0x103E8
+#define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8
+#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
+#define B_BE_SCHEDULE_ERR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
+#define B_BE_SCHEDULE_ERR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
+
#define R_BE_PORT_CFG_P0 0x10400
#define R_BE_PORT_CFG_P0_C1 0x14400
#define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18)
@@ -4677,6 +5434,248 @@
#define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4
#define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0)
+#define R_BE_PTCL_IMR_2 0x108B8
+#define R_BE_PTCL_IMR_2_C1 0x148B8
+#define B_BE_NO_TRX_TIMEOUT_IMR BIT(1)
+#define B_BE_TX_IDLE_TIMEOUT_IMR BIT(0)
+#define B_BE_PTCL_IMR_2_CLR B_BE_TX_IDLE_TIMEOUT_IMR
+#define B_BE_PTCL_IMR_2_SET 0
+
+#define R_BE_PTCL_IMR0 0x108C0
+#define R_BE_PTCL_IMR0_C1 0x148C0
+#define B_BE_PTCL_ERROR_FLAG_IMR BIT(31)
+#define B_BE_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
+#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
+#define B_BE_PTCL_IMR0_CLR (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
+ B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
+ B_BE_PTCL_ERROR_FLAG_IMR)
+#define B_BE_PTCL_IMR0_SET (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
+ B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
+ B_BE_PTCL_ERROR_FLAG_IMR)
+
+#define R_BE_PTCL_IMR1 0x108C8
+#define R_BE_PTCL_IMR1_C1 0x148C8
+#define B_BE_F2PCMD_PKTID_IMR BIT(30)
+#define B_BE_F2PCMD_RD_PKTID_IMR BIT(29)
+#define B_BE_F2PCMD_ASSIGN_PKTID_IMR BIT(28)
+#define B_BE_F2PCMD_USER_ALLC_IMR BIT(27)
+#define B_BE_RX_SPF_U0_PKTID_IMR BIT(26)
+#define B_BE_TX_SPF_U1_PKTID_IMR BIT(25)
+#define B_BE_TX_SPF_U2_PKTID_IMR BIT(24)
+#define B_BE_TX_SPF_U3_PKTID_IMR BIT(23)
+#define B_BE_TX_RECORD_PKTID_IMR BIT(22)
+#define B_BE_TWTSP_QSEL_IMR BIT(14)
+#define B_BE_F2P_RLS_CTN_SEL_IMR BIT(13)
+#define B_BE_BCNQ_ORDER_IMR BIT(12)
+#define B_BE_Q_PKTID_IMR BIT(11)
+#define B_BE_D_PKTID_IMR BIT(10)
+#define B_BE_TXPRT_FULL_DROP_IMR BIT(9)
+#define B_BE_F2PCMDRPT_FULL_DROP_IMR BIT(8)
+#define B_BE_PTCL_IMR1_CLR (B_BE_F2PCMDRPT_FULL_DROP_IMR | \
+ B_BE_TXPRT_FULL_DROP_IMR | \
+ B_BE_D_PKTID_IMR | \
+ B_BE_Q_PKTID_IMR | \
+ B_BE_BCNQ_ORDER_IMR | \
+ B_BE_F2P_RLS_CTN_SEL_IMR | \
+ B_BE_TWTSP_QSEL_IMR | \
+ B_BE_TX_RECORD_PKTID_IMR | \
+ B_BE_TX_SPF_U3_PKTID_IMR | \
+ B_BE_TX_SPF_U2_PKTID_IMR | \
+ B_BE_TX_SPF_U1_PKTID_IMR | \
+ B_BE_RX_SPF_U0_PKTID_IMR | \
+ B_BE_F2PCMD_USER_ALLC_IMR | \
+ B_BE_F2PCMD_ASSIGN_PKTID_IMR | \
+ B_BE_F2PCMD_RD_PKTID_IMR | \
+ B_BE_F2PCMD_PKTID_IMR)
+#define B_BE_PTCL_IMR1_SET B_BE_F2PCMD_USER_ALLC_IMR
+
+#define R_BE_RX_ERROR_FLAG_IMR 0x10C04
+#define R_BE_RX_ERROR_FLAG_IMR_C1 0x14C04
+#define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31)
+#define B_BE_RX_GET_NULL_PKT_ERROR_IMR BIT(30)
+#define B_BE_RX_RU0_FSM_HANG_ERROR_IMR BIT(29)
+#define B_BE_RX_RU1_FSM_HANG_ERROR_IMR BIT(28)
+#define B_BE_RX_RU2_FSM_HANG_ERROR_IMR BIT(27)
+#define B_BE_RX_RU3_FSM_HANG_ERROR_IMR BIT(26)
+#define B_BE_RX_RU4_FSM_HANG_ERROR_IMR BIT(25)
+#define B_BE_RX_RU5_FSM_HANG_ERROR_IMR BIT(24)
+#define B_BE_RX_RU6_FSM_HANG_ERROR_IMR BIT(23)
+#define B_BE_RX_RU7_FSM_HANG_ERROR_IMR BIT(22)
+#define B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR BIT(21)
+#define B_BE_RX_CSI_FSM_HANG_ERROR_IMR BIT(20)
+#define B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR BIT(19)
+#define B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR BIT(18)
+#define B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR BIT(17)
+#define B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR BIT(16)
+#define B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR BIT(15)
+#define B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR BIT(14)
+#define B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR BIT(13)
+#define B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR BIT(12)
+#define B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR BIT(11)
+#define B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR BIT(10)
+#define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR BIT(9)
+#define B_BE_RX_CSI_ZERO_LENGTH_ERROR_IMR BIT(8)
+#define B_BE_PLE_DATA_OPT_FSM_HANG_IMR BIT(7)
+#define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG_IMR BIT(6)
+#define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG_IMR BIT(5)
+#define B_BE_PLE_WD_OPT_FSM_HANG_IMR BIT(4)
+#define B_BE_PLE_ENQ_FSM_HANG_IMR BIT(3)
+#define B_BE_RXDATA_ENQUE_ORDER_ERROR_IMR BIT(2)
+#define B_BE_RXSTS_ENQUE_ORDER_ERROR_IMR BIT(1)
+#define B_BE_RX_CSI_PKT_NUM_ERROR_IMR BIT(0)
+#define B_BE_RX_ERROR_FLAG_IMR_CLR (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_GET_NULL_PKT_ERROR_IMR)
+#define B_BE_RX_ERROR_FLAG_IMR_SET (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_GET_NULL_PKT_ERROR_IMR)
+
+#define R_BE_TX_ERROR_FLAG_IMR 0x10C70
+#define R_BE_TX_ERROR_FLAG_IMR_C1 0x14C70
+#define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31)
+#define B_BE_TX_RU1_FSM_HANG_ERROR_IMR BIT(30)
+#define B_BE_TX_RU2_FSM_HANG_ERROR_IMR BIT(29)
+#define B_BE_TX_RU3_FSM_HANG_ERROR_IMR BIT(28)
+#define B_BE_TX_RU4_FSM_HANG_ERROR_IMR BIT(27)
+#define B_BE_TX_RU5_FSM_HANG_ERROR_IMR BIT(26)
+#define B_BE_TX_RU6_FSM_HANG_ERROR_IMR BIT(25)
+#define B_BE_TX_RU7_FSM_HANG_ERROR_IMR BIT(24)
+#define B_BE_TX_RU8_FSM_HANG_ERROR_IMR BIT(23)
+#define B_BE_TX_RU9_FSM_HANG_ERROR_IMR BIT(22)
+#define B_BE_TX_RU10_FSM_HANG_ERROR_IMR BIT(21)
+#define B_BE_TX_RU11_FSM_HANG_ERROR_IMR BIT(20)
+#define B_BE_TX_RU12_FSM_HANG_ERROR_IMR BIT(19)
+#define B_BE_TX_RU13_FSM_HANG_ERROR_IMR BIT(18)
+#define B_BE_TX_RU14_FSM_HANG_ERROR_IMR BIT(17)
+#define B_BE_TX_RU15_FSM_HANG_ERROR_IMR BIT(16)
+#define B_BE_TX_CSI_FSM_HANG_ERROR_IMR BIT(15)
+#define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR BIT(14)
+#define B_BE_TX_ERROR_FLAG_IMR_CLR (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
+#define B_BE_TX_ERROR_FLAG_IMR_SET (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
+ B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
+
+#define R_BE_RX_ERROR_FLAG_IMR_1 0x10C88
+#define R_BE_RX_ERROR_FLAG_IMR_1_C1 0x14C88
+#define B_BE_RX_RU8_FSM_HANG_ERROR_IMR BIT(29)
+#define B_BE_RX_RU9_FSM_HANG_ERROR_IMR BIT(28)
+#define B_BE_RX_RU10_FSM_HANG_ERROR_IMR BIT(27)
+#define B_BE_RX_RU11_FSM_HANG_ERROR_IMR BIT(26)
+#define B_BE_RX_RU12_FSM_HANG_ERROR_IMR BIT(25)
+#define B_BE_RX_RU13_FSM_HANG_ERROR_IMR BIT(24)
+#define B_BE_RX_RU14_FSM_HANG_ERROR_IMR BIT(23)
+#define B_BE_RX_RU15_FSM_HANG_ERROR_IMR BIT(22)
+#define B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR BIT(17)
+#define B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR BIT(16)
+#define B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR BIT(15)
+#define B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR BIT(14)
+#define B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR BIT(13)
+#define B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR BIT(12)
+#define B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR BIT(11)
+#define B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR BIT(10)
+#define B_BE_TX_ERROR_FLAG_IMR_1_CLR (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
+#define B_BE_TX_ERROR_FLAG_IMR_1_SET (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
+ B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
+ B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
+
#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08
#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08
#define B_BE_TSFT_OFS_MASK GENMASK(31, 16)
@@ -4684,6 +5683,64 @@
#define B_BE_UPD_HGQMD BIT(1)
#define B_BE_UPD_TIMIE BIT(0)
+#define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC
+#define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC
+#define B_BE_WMAC_FTM_TIMEOUT_MODE BIT(30)
+#define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24)
+#define B_BE_WMAC_MODE BIT(22)
+#define B_BE_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
+#define B_BE_RMAC_BFMER BIT(9)
+#define B_BE_RMAC_FTM BIT(8)
+#define B_BE_RMAC_CSI BIT(7)
+#define B_BE_TMAC_MIMO_CTRL BIT(6)
+#define B_BE_TMAC_RXTB BIT(5)
+#define B_BE_TMAC_HWSIGB_GEN BIT(4)
+#define B_BE_TMAC_TXPLCP BIT(3)
+#define B_BE_TMAC_RESP BIT(2)
+#define B_BE_TMAC_TXCTL BIT(1)
+#define B_BE_TMAC_MACTX BIT(0)
+#define B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR (B_BE_TMAC_MACTX | \
+ B_BE_TMAC_TXCTL | \
+ B_BE_TMAC_RESP | \
+ B_BE_TMAC_TXPLCP | \
+ B_BE_TMAC_HWSIGB_GEN | \
+ B_BE_TMAC_RXTB | \
+ B_BE_TMAC_MIMO_CTRL | \
+ B_BE_RMAC_CSI | \
+ B_BE_RMAC_FTM | \
+ B_BE_RMAC_BFMER)
+#define B_BE_TRXPTCL_ERROR_INDICA_MASK_SET (B_BE_TMAC_MACTX | \
+ B_BE_TMAC_TXCTL | \
+ B_BE_TMAC_RESP | \
+ B_BE_TMAC_TXPLCP | \
+ B_BE_TMAC_HWSIGB_GEN | \
+ B_BE_TMAC_RXTB | \
+ B_BE_TMAC_MIMO_CTRL | \
+ B_BE_RMAC_CSI | \
+ B_BE_RMAC_FTM | \
+ B_BE_RMAC_BFMER)
+
+#define R_BE_PHYINFO_ERR_IMR_V1 0x110F8
+#define R_BE_PHYINFO_ERR_IMR_V1_C1 0x150F8
+#define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)
+#define B_BE_PHYINTF_RXTB_EN_PHASE_MASK GENMASK(29, 28)
+#define B_BE_PHYINTF_MIMO_WIDTH_MASK GENMASK(27, 26)
+#define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24)
+#define B_BE_PHYINTF_TIMEOUT_THR_V1_MASK GENMASK(21, 16)
+#define B_BE_CSI_ON_TIMEOUT_EN BIT(5)
+#define B_BE_STS_ON_TIMEOUT_EN BIT(4)
+#define B_BE_DATA_ON_TIMEOUT_EN BIT(3)
+#define B_BE_OFDM_CCA_TIMEOUT_EN BIT(2)
+#define B_BE_CCK_CCA_TIMEOUT_EN BIT(1)
+#define B_BE_PHY_TXON_TIMEOUT_EN BIT(0)
+#define B_BE_PHYINFO_ERR_IMR_V1_CLR (B_BE_PHY_TXON_TIMEOUT_EN | \
+ B_BE_CCK_CCA_TIMEOUT_EN | \
+ B_BE_OFDM_CCA_TIMEOUT_EN | \
+ B_BE_DATA_ON_TIMEOUT_EN | \
+ B_BE_STS_ON_TIMEOUT_EN | \
+ B_BE_CSI_ON_TIMEOUT_EN)
+#define B_BE_PHYINFO_ERR_IMR_V1_SET 0
+
#define R_BE_BFMEE_RESP_OPTION 0x11180
#define R_BE_BFMEE_RESP_OPTION_C1 0x15180
#define B_BE_BFMEE_CSI_SEC_TYPE_SH 20
@@ -4764,6 +5821,77 @@
#define B_BE_CSIPRT_HESU_AID_EN BIT(25)
#define B_BE_CSIPRT_VHTSU_AID_EN BIT(24)
+#define R_BE_RX_ERR_IMR 0x114F8
+#define R_BE_RX_ERR_IMR_C1 0x154F8
+#define B_BE_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
+#define B_BE_RX_ERR_STS_ACT_TO_MSK BIT(8)
+#define B_BE_RX_ERR_CSI_ACT_TO_MSK BIT(7)
+#define B_BE_RX_ERR_ACT_TO_MSK BIT(6)
+#define B_BE_CSI_DATAON_ASSERT_TO_MSK BIT(5)
+#define B_BE_DATAON_ASSERT_TO_MSK BIT(4)
+#define B_BE_CCA_ASSERT_TO_MSK BIT(3)
+#define B_BE_RX_ERR_DMA_TO_MSK BIT(2)
+#define B_BE_RX_ERR_DATA_TO_MSK BIT(1)
+#define B_BE_RX_ERR_CCA_TO_MSK BIT(0)
+#define B_BE_RX_ERR_IMR_CLR (B_BE_RX_ERR_CCA_TO_MSK | \
+ B_BE_RX_ERR_DATA_TO_MSK | \
+ B_BE_RX_ERR_DMA_TO_MSK | \
+ B_BE_CCA_ASSERT_TO_MSK | \
+ B_BE_DATAON_ASSERT_TO_MSK | \
+ B_BE_CSI_DATAON_ASSERT_TO_MSK | \
+ B_BE_RX_ERR_ACT_TO_MSK | \
+ B_BE_RX_ERR_CSI_ACT_TO_MSK | \
+ B_BE_RX_ERR_STS_ACT_TO_MSK | \
+ B_BE_RX_ERR_TRIG_ACT_TO_MSK)
+#define B_BE_RX_ERR_IMR_SET (B_BE_RX_ERR_ACT_TO_MSK | \
+ B_BE_RX_ERR_STS_ACT_TO_MSK | \
+ B_BE_RX_ERR_TRIG_ACT_TO_MSK)
+
+#define R_BE_RESP_IMR 0x11884
+#define R_BE_RESP_IMR_C1 0x15884
+#define B_BE_RESP_TBL_FLAG_ERR_ISR_EN BIT(17)
+#define B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN BIT(16)
+#define B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN BIT(15)
+#define B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN BIT(14)
+#define B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN BIT(13)
+#define B_BE_RESP_PLDID_RDY_ERR_ISR_EN BIT(12)
+#define B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN BIT(11)
+#define B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN BIT(10)
+#define B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN BIT(9)
+#define B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN BIT(8)
+#define B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN BIT(6)
+#define B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN BIT(5)
+#define B_BE_RESP_TXCMD_TBL_ERR_ISR_EN BIT(4)
+#define B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN BIT(3)
+#define B_BE_RESP_INITCMD_RESERVD_PAGE_ABORT_ERR_ISR_EN BIT(2)
+#define B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN BIT(1)
+#define B_BE_RESP_DMAC_PROC_ERR_ISR_EN BIT(0)
+#define B_BE_RESP_IMR_CLR (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
+ B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN | \
+ B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN | \
+ B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN | \
+ B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
+ B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
+ B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN | \
+ B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN | \
+ B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
+ B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
+#define B_BE_RESP_IMR_SET (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
+ B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
+ B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
+ B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
+ B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
+ B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
+ B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
+
#define R_BE_PWR_MODULE 0x11900
#define R_BE_PWR_MODULE_C1 0x15900
@@ -4775,6 +5903,12 @@
#define R_BE_PWR_RU_LMT 0x12048
#define R_BE_PWR_RU_LMT_MAX 0x120E4
+#define R_BE_C0_TXPWR_IMR 0x128E0
+#define R_BE_C0_TXPWR_IMR_C1 0x168E0
+#define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
+#define B_BE_C0_TXPWR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
+#define B_BE_C0_TXPWR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
+
#define CMAC1_START_ADDR_BE 0x14000
#define CMAC1_END_ADDR_BE 0x17FFF
@@ -2454,6 +2454,8 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.dcfo_comp = &rtw8851b_dcfo_comp,
.dcfo_comp_sft = 12,
.imr_info = &rtw8851b_imr_info,
+ .imr_dmac_table = NULL,
+ .imr_cmac_table = NULL,
.rrsr_cfgs = &rtw8851b_rrsr_cfgs,
.bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
.bss_clr_map_reg = R_BSS_CLR_MAP_V1,
@@ -2191,6 +2191,8 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.dcfo_comp = &rtw8852a_dcfo_comp,
.dcfo_comp_sft = 10,
.imr_info = &rtw8852a_imr_info,
+ .imr_dmac_table = NULL,
+ .imr_cmac_table = NULL,
.rrsr_cfgs = &rtw8852a_rrsr_cfgs,
.bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
.bss_clr_map_reg = R_BSS_CLR_MAP,
@@ -2625,6 +2625,8 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.dcfo_comp = &rtw8852b_dcfo_comp,
.dcfo_comp_sft = 10,
.imr_info = &rtw8852b_imr_info,
+ .imr_dmac_table = NULL,
+ .imr_cmac_table = NULL,
.rrsr_cfgs = &rtw8852b_rrsr_cfgs,
.bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
.bss_clr_map_reg = R_BSS_CLR_MAP_V1,
@@ -2964,6 +2964,8 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.dcfo_comp = &rtw8852c_dcfo_comp,
.dcfo_comp_sft = 12,
.imr_info = &rtw8852c_imr_info,
+ .imr_dmac_table = NULL,
+ .imr_cmac_table = NULL,
.rrsr_cfgs = &rtw8852c_rrsr_cfgs,
.bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
.bss_clr_map_reg = R_BSS_CLR_MAP,
@@ -63,6 +63,62 @@ static const struct rtw89_dle_mem rtw8922a_dle_mem_pcie[] = {
NULL},
};
+static const struct rtw89_reg_imr rtw8922a_imr_dmac_regs[] = {
+ {R_BE_DISP_HOST_IMR, B_BE_DISP_HOST_IMR_CLR, B_BE_DISP_HOST_IMR_SET},
+ {R_BE_DISP_CPU_IMR, B_BE_DISP_CPU_IMR_CLR, B_BE_DISP_CPU_IMR_SET},
+ {R_BE_DISP_OTHER_IMR, B_BE_DISP_OTHER_IMR_CLR, B_BE_DISP_OTHER_IMR_SET},
+ {R_BE_PKTIN_ERR_IMR, B_BE_PKTIN_ERR_IMR_CLR, B_BE_PKTIN_ERR_IMR_SET},
+ {R_BE_INTERRUPT_MASK_REG, B_BE_INTERRUPT_MASK_REG_CLR, B_BE_INTERRUPT_MASK_REG_SET},
+ {R_BE_MLO_ERR_IDCT_IMR, B_BE_MLO_ERR_IDCT_IMR_CLR, B_BE_MLO_ERR_IDCT_IMR_SET},
+ {R_BE_MPDU_TX_ERR_IMR, B_BE_MPDU_TX_ERR_IMR_CLR, B_BE_MPDU_TX_ERR_IMR_SET},
+ {R_BE_MPDU_RX_ERR_IMR, B_BE_MPDU_RX_ERR_IMR_CLR, B_BE_MPDU_RX_ERR_IMR_SET},
+ {R_BE_SEC_ERROR_IMR, B_BE_SEC_ERROR_IMR_CLR, B_BE_SEC_ERROR_IMR_SET},
+ {R_BE_CPUIO_ERR_IMR, B_BE_CPUIO_ERR_IMR_CLR, B_BE_CPUIO_ERR_IMR_SET},
+ {R_BE_WDE_ERR_IMR, B_BE_WDE_ERR_IMR_CLR, B_BE_WDE_ERR_IMR_SET},
+ {R_BE_WDE_ERR1_IMR, B_BE_WDE_ERR1_IMR_CLR, B_BE_WDE_ERR1_IMR_SET},
+ {R_BE_PLE_ERR_IMR, B_BE_PLE_ERR_IMR_CLR, B_BE_PLE_ERR_IMR_SET},
+ {R_BE_PLE_ERRFLAG1_IMR, B_BE_PLE_ERRFLAG1_IMR_CLR, B_BE_PLE_ERRFLAG1_IMR_SET},
+ {R_BE_WDRLS_ERR_IMR, B_BE_WDRLS_ERR_IMR_CLR, B_BE_WDRLS_ERR_IMR_SET},
+ {R_BE_TXPKTCTL_B0_ERRFLAG_IMR, B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR,
+ B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET},
+ {R_BE_TXPKTCTL_B1_ERRFLAG_IMR, B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR,
+ B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET},
+ {R_BE_BBRPT_COM_ERR_IMR, B_BE_BBRPT_COM_ERR_IMR_CLR, B_BE_BBRPT_COM_ERR_IMR_SET},
+ {R_BE_BBRPT_CHINFO_ERR_IMR, B_BE_BBRPT_CHINFO_ERR_IMR_CLR,
+ B_BE_BBRPT_CHINFO_ERR_IMR_SET},
+ {R_BE_BBRPT_DFS_ERR_IMR, B_BE_BBRPT_DFS_ERR_IMR_CLR, B_BE_BBRPT_DFS_ERR_IMR_SET},
+ {R_BE_LA_ERRFLAG_IMR, B_BE_LA_ERRFLAG_IMR_CLR, B_BE_LA_ERRFLAG_IMR_SET},
+ {R_BE_CH_INFO_DBGFLAG_IMR, B_BE_CH_INFO_DBGFLAG_IMR_CLR, B_BE_CH_INFO_DBGFLAG_IMR_SET},
+ {R_BE_PLRLS_ERR_IMR, B_BE_PLRLS_ERR_IMR_CLR, B_BE_PLRLS_ERR_IMR_SET},
+ {R_BE_HAXI_IDCT_MSK, B_BE_HAXI_IDCT_MSK_CLR, B_BE_HAXI_IDCT_MSK_SET},
+};
+
+static const struct rtw89_imr_table rtw8922a_imr_dmac_table = {
+ .regs = rtw8922a_imr_dmac_regs,
+ .n_regs = ARRAY_SIZE(rtw8922a_imr_dmac_regs),
+};
+
+static const struct rtw89_reg_imr rtw8922a_imr_cmac_regs[] = {
+ {R_BE_RESP_IMR, B_BE_RESP_IMR_CLR, B_BE_RESP_IMR_SET},
+ {R_BE_RX_ERROR_FLAG_IMR, B_BE_RX_ERROR_FLAG_IMR_CLR, B_BE_RX_ERROR_FLAG_IMR_SET},
+ {R_BE_TX_ERROR_FLAG_IMR, B_BE_TX_ERROR_FLAG_IMR_CLR, B_BE_TX_ERROR_FLAG_IMR_SET},
+ {R_BE_RX_ERROR_FLAG_IMR_1, B_BE_TX_ERROR_FLAG_IMR_1_CLR, B_BE_TX_ERROR_FLAG_IMR_1_SET},
+ {R_BE_PTCL_IMR1, B_BE_PTCL_IMR1_CLR, B_BE_PTCL_IMR1_SET},
+ {R_BE_PTCL_IMR0, B_BE_PTCL_IMR0_CLR, B_BE_PTCL_IMR0_SET},
+ {R_BE_PTCL_IMR_2, B_BE_PTCL_IMR_2_CLR, B_BE_PTCL_IMR_2_SET},
+ {R_BE_SCHEDULE_ERR_IMR, B_BE_SCHEDULE_ERR_IMR_CLR, B_BE_SCHEDULE_ERR_IMR_SET},
+ {R_BE_C0_TXPWR_IMR, B_BE_C0_TXPWR_IMR_CLR, B_BE_C0_TXPWR_IMR_SET},
+ {R_BE_TRXPTCL_ERROR_INDICA_MASK, B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR,
+ B_BE_TRXPTCL_ERROR_INDICA_MASK_SET},
+ {R_BE_RX_ERR_IMR, B_BE_RX_ERR_IMR_CLR, B_BE_RX_ERR_IMR_SET},
+ {R_BE_PHYINFO_ERR_IMR_V1, B_BE_PHYINFO_ERR_IMR_V1_CLR, B_BE_PHYINFO_ERR_IMR_V1_SET},
+};
+
+static const struct rtw89_imr_table rtw8922a_imr_cmac_table = {
+ .regs = rtw8922a_imr_cmac_regs,
+ .n_regs = ARRAY_SIZE(rtw8922a_imr_cmac_regs),
+};
+
static const struct rtw89_efuse_block_cfg rtw8922a_efuse_blocks[] = {
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
@@ -399,6 +455,8 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.dcfo_comp = NULL,
.dcfo_comp_sft = 0,
.imr_info = NULL,
+ .imr_dmac_table = &rtw8922a_imr_dmac_table,
+ .imr_cmac_table = &rtw8922a_imr_cmac_table,
.bss_clr_vld = {R_BSS_CLR_VLD_V2, B_BSS_CLR_VLD0_V2},
.bss_clr_map_reg = R_BSS_CLR_MAP_V2,
.dma_ch_mask = 0,
To activate SER (system error recovery) in firmware, we have to configure IMR to trigger interrupts, and then SER can check registers to know if it need to reset hardware or notify driver to re-configure whole settings. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> --- drivers/net/wireless/realtek/rtw89/core.h | 13 + drivers/net/wireless/realtek/rtw89/reg.h | 1134 +++++++++++++++++ drivers/net/wireless/realtek/rtw89/rtw8851b.c | 2 + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 2 + drivers/net/wireless/realtek/rtw89/rtw8852b.c | 2 + drivers/net/wireless/realtek/rtw89/rtw8852c.c | 2 + drivers/net/wireless/realtek/rtw89/rtw8922a.c | 58 + 7 files changed, 1213 insertions(+)