From patchwork Thu Sep 9 08:15:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shayne Chen X-Patchwork-Id: 509063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 128D7C433F5 for ; Thu, 9 Sep 2021 08:15:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0AD260FE3 for ; Thu, 9 Sep 2021 08:15:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230072AbhIIIQb (ORCPT ); Thu, 9 Sep 2021 04:16:31 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:44730 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229876AbhIIIQb (ORCPT ); Thu, 9 Sep 2021 04:16:31 -0400 X-UUID: 21fba95f4686407f8bbbf4b79701b451-20210909 X-UUID: 21fba95f4686407f8bbbf4b79701b451-20210909 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1881140079; Thu, 09 Sep 2021 16:15:20 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 9 Sep 2021 16:15:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 9 Sep 2021 16:15:19 +0800 From: Shayne Chen To: Felix Fietkau CC: linux-wireless , Lorenzo Bianconi , Ryder Lee , Evelyn Tsai , linux-mediatek , Shayne Chen Subject: [PATCH v4 7/8] mt76: mt7915: set VTA bit in tx descriptor Date: Thu, 9 Sep 2021 16:15:11 +0800 Message-ID: <20210909081512.5037-7-shayne.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210909081512.5037-1-shayne.chen@mediatek.com> References: <20210909081512.5037-1-shayne.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org The VTA (Valid for Txd Arrival time) bit should be set in tx descriptor, which is necessary for WM fw to schedule SPL (station priority list) normally before generating txcmd. If it's not set, some unexpected wcids may be involved in SPL. Suggested-by: Nelson Chang Signed-off-by: Shayne Chen --- drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index 1b8e37e265cb..497ae9935116 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -1034,7 +1034,7 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, FIELD_PREP(MT_TXD0_Q_IDX, q_idx); txwi[0] = cpu_to_le32(val); - val = MT_TXD1_LONG_FORMAT | + val = MT_TXD1_LONG_FORMAT | MT_TXD1_VTA | FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);