diff --git a/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h b/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h
new file mode 100644
index 000000000000..43bb07cef00a
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_DFS_DB_H
+#define CL_DFS_DB_H
+
+#include "dfs/radar.h"
+#include "utils/timer.h"
+
+#define CL_DFS_MAX_TBL_LINE       11    /* Radar Table Max Line */
+#define CL_DFS_MAX_PULSE          4     /* Max Pulses per Interrupt */
+#define CL_DFS_PULSE_BUF_SIZE     64    /* Radar Pulse buffer size */
+#define CL_DFS_PULSE_BUF_MASK     0x03F /* Radar Pulse buffer cyclic mask */
+#define CL_DFS_PULSE_WINDOW       100   /* Radar Pulse search window [ms] */
+#define CL_DFS_MIN_PULSE_TRIG     1     /* Minimum Pulse trigger num */
+#define CL_DFS_MAX_20MHZ_CH       25    /* Maximum 20MHz channels */
+#define CL_DFS_MIN_CH             52    /* Min DFS channel */
+#define CL_DFS_MAX_CH             144   /* Max DFS channel */
+#define CL_DFS_MIN_WEATHER_CH     120   /* Min DFS weather channel */
+#define CL_DFS_MAX_WEATHER_CH     128   /* Max DFS weather channel */
+#define CL_DFS_CAC_TIME           60    /* DFS CAC Time */
+#define CL_DFS_WEATHER_CAC_TIME   600   /* DFS weather channel CAC Time */
+#define CL_DFS_VALIDATION_TIME    1800  /* Validation time */
+#define CL_DFS_CE_CSA_CNT         10    /* According to CE regulation must leave within 1 sec */
+#define CL_DFS_LONG_MIN_WIDTH     20    /* Min Long Pulse Width */
+#define CL_DFS_LONG_FALSE_WIDTH   10    /* Low width signals indicates of false detections */
+#define CL_DFS_LONG_FALSE_IND     6     /* False indication while searching for long sequence */
+#define CL_DFS_FCC_CSA_CNT        2     /* According to FCC regulation must leave within 200ms */
+#define CL_DFS_SAFE_WIDTH         10    /* False detection not expected for high width signals */
+#define CL_DFS_BUF_SIZE           128   /* Max buffer size for loading channels DBs from NVRAM */
+#define CL_DFS_STAGGERED_CHEC_LEN 4     /* Staggered check length */
+#define CL_DFS_ONE_MINUTE         60    /* One minute [s] */
+#define CL_DFS_ONE_MINUTE_MS      60000 /* One minute [ms] */
+#define CL_DFS_ONE_SEC_MS         1000  /* One Second in [ms] */
+#define CL_DFS_THREE_SEC_MS       3000  /* Three Second in [ms] */
+#define CL_DFS_FIVE_SEC_MS        5000  /* Five Second in [ms] */
+#define CL_DFS_TEN_SEC_MS         10000 /* Twn Seconds in [ms] */
+#define CL_DFS_MIN_IDLE           10    /* Minimum consecutive idle decisions to start OCC */
+#define CL_DFS_CONCEAL_CNT        10     /* Maximum concealed pulses search */
+#define CL_DFS_FILTER_DELAY       100   /* Delay the decision by 100ms */
+#define CL_DFS_FILTER_PRI_MARGIN  10    /* PRI search margin */
+#define CL_DFS_LTP_PPB_MARGIN     2     /* Low TP PPB margin */
+#define CL_DFS_MAX_STAGGERED      3     /* Max Staggered patterns */
+
+enum cl_radar_waveform {
+       RADAR_WAVEFORM_SHORT,
+       RADAR_WAVEFORM_LONG,
+       RADAR_WAVEFORM_STAGGERED,
+       RADAR_WAVEFORM_SEVERE
+};
+
+struct cl_radar_type {
+       u8 id;
+       s32 min_width;
+       s32 max_width;
+       s32 tol_width;
+       s32 min_pri;
+       s32 max_pri;
+       s32 tol_pri;
+       s32 tol_freq;
+       u8 min_burst;
+       u8 ppb;
+       u8 trig_count;
+       enum cl_radar_waveform waveform;
+};
+
+struct cl_dfs_pulse {
+       s32 freq  : 8;      /* Radar Frequency offset [units of 4MHz] */
+       u32 fom   : 8;      /* Figure of Merit */
+       u32 width : 8;      /* Pulse Width [units of 2 micro sec] */
+       u32 occ   : 1;      /* OCC indication for Primary/Secondary channel */
+       u32 res1  : 7;      /* Reserve */
+       u32 pri   : 16;     /* Pulse Repetition Frequency */
+       u32 res2  : 16;
+       unsigned long time; /* Pulse Receive Time */
+};
+
+struct cl_dfs_db {
+       bool en;
+
+       struct {
+               bool started;
+               bool requested;
+       } cac;
+
+       enum cl_dbg_level dbg_lvl;
+       enum cl_reg_standard dfs_standard;
+       struct cl_radar_type *radar_type;
+       u8 csa_cnt;
+
+       u8 min_pulse_eeq;
+       u8 buf_idx;
+       u8 radar_type_cnt;
+       u16 search_window;
+       u16 last_pri;
+       u16 max_interrupt_diff;
+       u32 pulse_cnt;
+       u32 severe_env_pulse_cnt;
+       struct cl_dfs_pulse dfs_pulse[CL_DFS_PULSE_BUF_SIZE];
+       struct cl_dfs_pulse pulse_buffer[CL_DFS_PULSE_BUF_SIZE];
+       u8 long_pulse_count;
+       u32 last_long_pulse_ts;
+       u8 short_pulse_count;
+       u8 long_pri_match_count;
+};
+
+#endif /* CL_DFS_DB_H */
