new file mode 100644
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_RC_H
+#define CL_REG_RC_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+#define REG_RIU_RC_BASE_ADDR 0x00485000
+
+/*
+ * @brief SW_CTRL register definition
+ * This register provides write access to the radio SPI interface register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 START_DONE 0
+ * 30 MORE 0
+ * 29 FASTWR_SPD 0
+ * 28 FASTWR_FORCE 0
+ * 27 FWR_HW_ENABLE 1
+ * 26 FWR_SW_ENABLE 1
+ * 25 FWR_ENABLE 1
+ * 24 RF_RESET_B 0
+ * 23:19 PRESCALER 0x1
+ * 16 READNOTWRITE 0
+ * 14:08 ADDRESS 0x0
+ * 07:00 DATA 0x0
+ * </pre>
+ */
+#define RIU_RC_SW_CTRL_ADDR (REG_RIU_RC_BASE_ADDR + 0x00000000)
+#define RIU_RC_SW_CTRL_OFFSET 0x00000000
+#define RIU_RC_SW_CTRL_INDEX 0x00000000
+#define RIU_RC_SW_CTRL_RESET 0x0E080000
+
+static inline void riu_rc_sw_ctrl_pack(struct cl_hw *cl_hw, u8 startdone, u8 more, u8 fastwrspd,
+ u8 fastwrforce, u8 fwrhwenable, u8 fwrswenable, u8 fwrenable,
+ u8 rfresetb, u8 prescaler, u8 readnotwrite, u8 address,
+ u8 data)
+{
+ ASSERT_ERR((((u32)more << 30) & ~((u32)0x40000000)) == 0);
+ ASSERT_ERR((((u32)fastwrspd << 29) & ~((u32)0x20000000)) == 0);
+ ASSERT_ERR((((u32)fastwrforce << 28) & ~((u32)0x10000000)) == 0);
+ ASSERT_ERR((((u32)fwrhwenable << 27) & ~((u32)0x08000000)) == 0);
+ ASSERT_ERR((((u32)fwrswenable << 26) & ~((u32)0x04000000)) == 0);
+ ASSERT_ERR((((u32)fwrenable << 25) & ~((u32)0x02000000)) == 0);
+ ASSERT_ERR((((u32)rfresetb << 24) & ~((u32)0x01000000)) == 0);
+ ASSERT_ERR((((u32)prescaler << 19) & ~((u32)0x00F80000)) == 0);
+ ASSERT_ERR((((u32)readnotwrite << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR((((u32)address << 8) & ~((u32)0x00007F00)) == 0);
+
+ cl_reg_write(cl_hw, RIU_RC_SW_CTRL_ADDR, ((u32)startdone << 31) | ((u32)more << 30) |
+ ((u32)fastwrspd << 29) | ((u32)fastwrforce << 28) | ((u32)fwrhwenable << 27) |
+ ((u32)fwrswenable << 26) | ((u32)fwrenable << 25) | ((u32)rfresetb << 24) |
+ ((u32)prescaler << 19) | ((u32)readnotwrite << 16) | ((u32)address << 8) |
+ ((u32)data << 0));
+}
+
+static inline u8 riu_rc_sw_ctrl_start_done_getf(struct cl_hw *cl_hw)
+{
+ u32 local_val = cl_reg_read(cl_hw, RIU_RC_SW_CTRL_ADDR);
+
+ return ((local_val & ((u32)0x80000000)) >> 31);
+}
+
+static inline u8 riu_rc_sw_ctrl_data_getf(struct cl_hw *cl_hw)
+{
+ u32 local_val = cl_reg_read(cl_hw, RIU_RC_SW_CTRL_ADDR);
+
+ return ((local_val & ((u32)0x000000FF)) >> 0);
+}
+
+/*
+ * @brief RF_LNA_LUT register definition
+ * These registers provide control of the RF LNA assertion by decoding each possible value the AGC
+ * LNA gain setting, from minimum LNA gain to maximum LNA gain. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 26:24 RFLNALUT6 0x6
+ * 22:20 RFLNALUT5 0x5
+ * 18:16 RFLNALUT4 0x4
+ * 14:12 RFLNALUT3 0x3
+ * 10:08 RFLNALUT2 0x2
+ * 06:04 RFLNALUT1 0x1
+ * 02:00 RFLNALUT0 0x0
+ * </pre>
+ */
+
+/* Field definitions */
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_MASK ((u32)0x07000000)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_LSB 24
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_MASK ((u32)0x00700000)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_LSB 20
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_MASK ((u32)0x00070000)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_LSB 16
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_MASK ((u32)0x00007000)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_LSB 12
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_MASK ((u32)0x00000700)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_LSB 8
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_MASK ((u32)0x00000070)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_LSB 4
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_WIDTH ((u32)0x00000003)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_MASK ((u32)0x00000007)
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_LSB 0
+#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_WIDTH ((u32)0x00000003)
+
+#endif /* CL_REG_RC_H */