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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 153/256] cl8k: add reg/reg_io_ctrl.h Date: Thu, 17 Jun 2021 16:00:40 +0000 Message-Id: <20210617160223.160998-154-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f8e2a7b5-caf2-4808-a1ac-08d931a9b5ee X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: syUN/sMJIk5a/dcBtHjY3nS1P41xtInn0IKPJqKNGI2eH3fvy8QRjARFmjPG+GKUQDcBcj7nw19QL4C6uusFlvcpOq3RGUxlofznwM4ruawLmfeZDQ2qNWacbESkZUUFchATN52v2jDUvtuJh1+x5CywfA2I5XHzwvPrFScNhgxu/4fSH7aflFqw2CWx7ec+xJM6A4Na9lSjvqN11GIeL8GaFDUvZT3VarF9g3lfbqoiWN1ulUTJp+AsXmjPM7f7JKwKnsnYIouIC9Nyq9OKfRwW5dE0x9u2IcGWHt9q0VaOTnGiDs2VpFg7hPFQ/FPlGp5rnGPhRs4H7+2lWNMjwPy7+XzbKlhE2/74cb8zPLC+pOIg6NvcipfBFdEgh2EZghKaDU03iUvqD6fuN9hz0ac24rUSaVjKUbUcEb/7OC7yPeqBCnY9zlCckASiHf3JCFGume/biAYJBC4ZwJ2HGnxF1vsc+1SnSEty1tu8kGtTwBY72ywZ4bz44bAw6oyz2QOdQX2MYQEmraPOpuhYpqR/73DiGP6NOc0UfUtry+7P1WN8Jrm+Ncum4FOkT6+dgeyjv1XQJCke8De84j14jDnFSW/ALibgehkVpGrymS/mABxZrp8gzo3F9Pnm34+i91j+wIkmaPXuS1uWP+bHB4ORwC2JNmirUaFTRlMOaUvJPZ88VjLgbTwF7ApYt/NyyGl4taZ8gK9/J8ztG1aCtw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fOce2VYE+rETWEeZpcy/XZxjpUcpe3hjjR5qZnTKDbRfr6kqg8jVMXMjWPjH5EPbYdVFiA/4KgrUfadwti76FNx1SnggDngfbZk0LEoQfTNm8P/9OZRe4LPYcwehkBJqHKaJ+GaxOGp9IUFI9/XPboCzcgS+gW+dtOVZJiYmA5Hs7i7mEdO16oxZjfgmrJ1/NnP7tkoXBIor47EhbR8wbQEEpjJffIbTtU602CO6vP57FYzCm6pSclEKi/ZSEGkBdi79bXtlzEbrOYaDvTOxWYSTFIQ+HBPgSTIgiYBVpLWMG/ET7XFaYWJtkEk3mbZhAidVVN9aQIs+5OjQ7XNowgfkT/mEigcBBagEo4gP1NakuR9EdqPMC/IxeocB3V1oHs39LF6A8nkjZFEBg//UWpXvecIvWxTeRud9gPbu53pBWPoEnX0i9+KaHqx+oUgS8YVy/gKTJp/zXfrQQHYvqlLkSo3HmxCc6dgx2qh6VkA2Dj2BSR+Ob9mQtBTW6vsylmg5Wly4xLaXC31xwHGx6z5jfXTy9ixq8uYHMFZvEiOxjYlbxCoOADFT8i+CHts6KLKBColk6fCOFtJ5djKdPZpRvqEJ9MFzdNQEWXxbfz4rNiBlFaWzAdqN36dAStgg+rKiUXwYus8BNeU88FPJcHXutD0BypjbWmze8vYF0OIdXa6IS3KTYpbsJq8h6C2xssvk30fJHaJutlrNVNsHoRcl4pkkVddswa+Nfi6YMkIkyYrCA1jw6C3oYWw4HqUKbdQ+khgQrpNSnOitGhq4J8LYMsoh4mouAjRTVgYYvkysThDFVoetEtCWFFD8yf9MiLtS9nWmVnrX61ygH7kbUDrmv6VFeLLgawkpDbg9dyNculxy+AB3EczNsr8NT7xyAjMB1R2IUL8hc3ZdYhebmZ6pQENbRR1AgwcZ3EBUVbym+mjF17udkg3hQu+knOIoIZNsbGaKqV0LlcK+fvS1WNk3CI53bLoOSe+RfDXuaeDxLsWdKSXBm2rw0owu4B6oKWAClH6Jv5oNmnnKCVVUBWGHlkRkT8DvxRv5UmcvkRyvyROZcR9q1T+JyRAcEsCRvRf03ONGFkWVzE4HnxPLmfMTr/aA4vF6fizt4qTGK1M3KludJd6SDEsWp91v7IJ7nUOoCfnLRWRaHy1Co47gvc+aOzh36ykzPCRZGsdpeRdixSL9dNpzqYBE0mDOlCYtW/z5p/B5/KM6UTXTTTuO+UWmn2rkCxfOHFCMIXHv68oU79RcvlnojxMgRGA61Tq3CPyy4MsyVbxhwBBjXl0bBppzhz48JaVVvTmK8vCTkii5LYTyV79bdBW7MpaEs8JJ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: f8e2a7b5-caf2-4808-a1ac-08d931a9b5ee X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:22.3683 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4QoRyIru0LsV03EloflpDhWJiJf0LACfqlqUIgPYe4iTQ7YN8qARRYe5BSdPmTqKt3p3rO6Wtcm+tL5UK+kevA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_io_ctrl.h | 1223 +++++++++++++++++ 1 file changed, 1223 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h b/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h new file mode 100644 index 000000000000..190a7a98ebd3 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h @@ -0,0 +1,1223 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_IO_CTRL_H +#define CL_REG_IO_CTRL_H + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_IO_CTRL_BASE_ADDR 0x007C7000 + +/* + * @brief RX_ACTIVE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000005C) +#define IO_CTRL_RX_ACTIVE_0_OFFSET 0x0000005C +#define IO_CTRL_RX_ACTIVE_0_INDEX 0x00000017 +#define IO_CTRL_RX_ACTIVE_0_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_RX_ACTIVE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_RX_ACTIVE_0_GPIO_IN_POS 13 +#define IO_CTRL_RX_ACTIVE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_RX_ACTIVE_0_GPIO_OUT_POS 12 +#define IO_CTRL_RX_ACTIVE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_RX_ACTIVE_0_GPIO_OE_POS 11 +#define IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_RX_ACTIVE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_RX_ACTIVE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_RX_ACTIVE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_RX_ACTIVE_0_SLEW_RATE_POS 8 +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_RX_ACTIVE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_RX_ACTIVE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief RX_ACTIVE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000060) +#define IO_CTRL_RX_ACTIVE_1_OFFSET 0x00000060 +#define IO_CTRL_RX_ACTIVE_1_INDEX 0x00000018 +#define IO_CTRL_RX_ACTIVE_1_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_1_ADDR, value); +} + +/* + * @brief RX_ACTIVE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000064) +#define IO_CTRL_RX_ACTIVE_2_OFFSET 0x00000064 +#define IO_CTRL_RX_ACTIVE_2_INDEX 0x00000019 +#define IO_CTRL_RX_ACTIVE_2_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_2_ADDR, value); +} + +/* + * @brief RX_ACTIVE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000068) +#define IO_CTRL_RX_ACTIVE_3_OFFSET 0x00000068 +#define IO_CTRL_RX_ACTIVE_3_INDEX 0x0000001A +#define IO_CTRL_RX_ACTIVE_3_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_3_ADDR, value); +} + +/* + * @brief RX_ACTIVE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000006C) +#define IO_CTRL_RX_ACTIVE_4_OFFSET 0x0000006C +#define IO_CTRL_RX_ACTIVE_4_INDEX 0x0000001B +#define IO_CTRL_RX_ACTIVE_4_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_4_ADDR, value); +} + +/* + * @brief RX_ACTIVE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000070) +#define IO_CTRL_RX_ACTIVE_5_OFFSET 0x00000070 +#define IO_CTRL_RX_ACTIVE_5_INDEX 0x0000001C +#define IO_CTRL_RX_ACTIVE_5_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_5_ADDR, value); +} + +/* + * @brief RX_ACTIVE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000074) +#define IO_CTRL_RX_ACTIVE_6_OFFSET 0x00000074 +#define IO_CTRL_RX_ACTIVE_6_INDEX 0x0000001D +#define IO_CTRL_RX_ACTIVE_6_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_6_ADDR, value); +} + +/* + * @brief RX_ACTIVE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000078) +#define IO_CTRL_RX_ACTIVE_7_OFFSET 0x00000078 +#define IO_CTRL_RX_ACTIVE_7_INDEX 0x0000001E +#define IO_CTRL_RX_ACTIVE_7_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_7_ADDR, value); +} + +/* + * @brief LNA_ENABLE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000007C) +#define IO_CTRL_LNA_ENABLE_0_OFFSET 0x0000007C +#define IO_CTRL_LNA_ENABLE_0_INDEX 0x0000001F +#define IO_CTRL_LNA_ENABLE_0_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_LNA_ENABLE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_LNA_ENABLE_0_GPIO_IN_POS 13 +#define IO_CTRL_LNA_ENABLE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_LNA_ENABLE_0_GPIO_OUT_POS 12 +#define IO_CTRL_LNA_ENABLE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_LNA_ENABLE_0_GPIO_OE_POS 11 +#define IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_LNA_ENABLE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_LNA_ENABLE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_LNA_ENABLE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_LNA_ENABLE_0_SLEW_RATE_POS 8 +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_LNA_ENABLE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_LNA_ENABLE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief LNA_ENABLE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000080) +#define IO_CTRL_LNA_ENABLE_1_OFFSET 0x00000080 +#define IO_CTRL_LNA_ENABLE_1_INDEX 0x00000020 +#define IO_CTRL_LNA_ENABLE_1_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_1_ADDR, value); +} + +/* + * @brief LNA_ENABLE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000084) +#define IO_CTRL_LNA_ENABLE_2_OFFSET 0x00000084 +#define IO_CTRL_LNA_ENABLE_2_INDEX 0x00000021 +#define IO_CTRL_LNA_ENABLE_2_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_2_ADDR, value); +} + +/* + * @brief LNA_ENABLE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000088) +#define IO_CTRL_LNA_ENABLE_3_OFFSET 0x00000088 +#define IO_CTRL_LNA_ENABLE_3_INDEX 0x00000022 +#define IO_CTRL_LNA_ENABLE_3_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_3_ADDR, value); +} + +/* + * @brief LNA_ENABLE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000008C) +#define IO_CTRL_LNA_ENABLE_4_OFFSET 0x0000008C +#define IO_CTRL_LNA_ENABLE_4_INDEX 0x00000023 +#define IO_CTRL_LNA_ENABLE_4_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_4_ADDR, value); +} + +/* + * @brief LNA_ENABLE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000090) +#define IO_CTRL_LNA_ENABLE_5_OFFSET 0x00000090 +#define IO_CTRL_LNA_ENABLE_5_INDEX 0x00000024 +#define IO_CTRL_LNA_ENABLE_5_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_5_ADDR, value); +} + +/* + * @brief LNA_ENABLE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000094) +#define IO_CTRL_LNA_ENABLE_6_OFFSET 0x00000094 +#define IO_CTRL_LNA_ENABLE_6_INDEX 0x00000025 +#define IO_CTRL_LNA_ENABLE_6_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_6_ADDR, value); +} + +/* + * @brief LNA_ENABLE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000098) +#define IO_CTRL_LNA_ENABLE_7_OFFSET 0x00000098 +#define IO_CTRL_LNA_ENABLE_7_INDEX 0x00000026 +#define IO_CTRL_LNA_ENABLE_7_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_7_ADDR, value); +} + +/* + * @brief LNA_ENABLE_8 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_8_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000009C) +#define IO_CTRL_LNA_ENABLE_8_OFFSET 0x0000009C +#define IO_CTRL_LNA_ENABLE_8_INDEX 0x00000027 +#define IO_CTRL_LNA_ENABLE_8_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_8_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_8_ADDR, value); +} + +/* + * @brief LNA_ENABLE_9 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_9_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A0) +#define IO_CTRL_LNA_ENABLE_9_OFFSET 0x000000A0 +#define IO_CTRL_LNA_ENABLE_9_INDEX 0x00000028 +#define IO_CTRL_LNA_ENABLE_9_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_9_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_9_ADDR, value); +} + +/* + * @brief LNA_ENABLE_10 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_10_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A4) +#define IO_CTRL_LNA_ENABLE_10_OFFSET 0x000000A4 +#define IO_CTRL_LNA_ENABLE_10_INDEX 0x00000029 +#define IO_CTRL_LNA_ENABLE_10_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_10_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_10_ADDR, value); +} + +/* + * @brief LNA_ENABLE_11 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_11_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A8) +#define IO_CTRL_LNA_ENABLE_11_OFFSET 0x000000A8 +#define IO_CTRL_LNA_ENABLE_11_INDEX 0x0000002A +#define IO_CTRL_LNA_ENABLE_11_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_11_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_11_ADDR, value); +} + +/* + * @brief PA_ENABLE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000AC) +#define IO_CTRL_PA_ENABLE_0_OFFSET 0x000000AC +#define IO_CTRL_PA_ENABLE_0_INDEX 0x0000002B +#define IO_CTRL_PA_ENABLE_0_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_PA_ENABLE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_PA_ENABLE_0_GPIO_IN_POS 13 +#define IO_CTRL_PA_ENABLE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_PA_ENABLE_0_GPIO_OUT_POS 12 +#define IO_CTRL_PA_ENABLE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_PA_ENABLE_0_GPIO_OE_POS 11 +#define IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_PA_ENABLE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_PA_ENABLE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_PA_ENABLE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_PA_ENABLE_0_SLEW_RATE_POS 8 +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_PA_ENABLE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_PA_ENABLE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief PA_ENABLE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B0) +#define IO_CTRL_PA_ENABLE_1_OFFSET 0x000000B0 +#define IO_CTRL_PA_ENABLE_1_INDEX 0x0000002C +#define IO_CTRL_PA_ENABLE_1_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_1_ADDR, value); +} + +/* + * @brief PA_ENABLE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B4) +#define IO_CTRL_PA_ENABLE_2_OFFSET 0x000000B4 +#define IO_CTRL_PA_ENABLE_2_INDEX 0x0000002D +#define IO_CTRL_PA_ENABLE_2_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_2_ADDR, value); +} + +/* + * @brief PA_ENABLE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B8) +#define IO_CTRL_PA_ENABLE_3_OFFSET 0x000000B8 +#define IO_CTRL_PA_ENABLE_3_INDEX 0x0000002E +#define IO_CTRL_PA_ENABLE_3_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_3_ADDR, value); +} + +/* + * @brief PA_ENABLE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000BC) +#define IO_CTRL_PA_ENABLE_4_OFFSET 0x000000BC +#define IO_CTRL_PA_ENABLE_4_INDEX 0x0000002F +#define IO_CTRL_PA_ENABLE_4_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_4_ADDR, value); +} + +/* + * @brief PA_ENABLE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C0) +#define IO_CTRL_PA_ENABLE_5_OFFSET 0x000000C0 +#define IO_CTRL_PA_ENABLE_5_INDEX 0x00000030 +#define IO_CTRL_PA_ENABLE_5_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_5_ADDR, value); +} + +/* + * @brief PA_ENABLE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C4) +#define IO_CTRL_PA_ENABLE_6_OFFSET 0x000000C4 +#define IO_CTRL_PA_ENABLE_6_INDEX 0x00000031 +#define IO_CTRL_PA_ENABLE_6_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_6_ADDR, value); +} + +/* + * @brief PA_ENABLE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C8) +#define IO_CTRL_PA_ENABLE_7_OFFSET 0x000000C8 +#define IO_CTRL_PA_ENABLE_7_INDEX 0x00000032 +#define IO_CTRL_PA_ENABLE_7_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_7_ADDR, value); +} + +/* + * @brief PA_ENABLE_8 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_8_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000CC) +#define IO_CTRL_PA_ENABLE_8_OFFSET 0x000000CC +#define IO_CTRL_PA_ENABLE_8_INDEX 0x00000033 +#define IO_CTRL_PA_ENABLE_8_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_8_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_8_ADDR, value); +} + +/* + * @brief PA_ENABLE_9 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_9_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D0) +#define IO_CTRL_PA_ENABLE_9_OFFSET 0x000000D0 +#define IO_CTRL_PA_ENABLE_9_INDEX 0x00000034 +#define IO_CTRL_PA_ENABLE_9_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_9_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_9_ADDR, value); +} + +/* + * @brief PA_ENABLE_10 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_10_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D4) +#define IO_CTRL_PA_ENABLE_10_OFFSET 0x000000D4 +#define IO_CTRL_PA_ENABLE_10_INDEX 0x00000035 +#define IO_CTRL_PA_ENABLE_10_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_10_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_10_ADDR, value); +} + +/* + * @brief PA_ENABLE_11 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_11_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D8) +#define IO_CTRL_PA_ENABLE_11_OFFSET 0x000000D8 +#define IO_CTRL_PA_ENABLE_11_INDEX 0x00000036 +#define IO_CTRL_PA_ENABLE_11_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_11_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_11_ADDR, value); +} + +/* + * @brief SPICLK register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_SPICLK_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000DC) +#define IO_CTRL_SPICLK_OFFSET 0x000000DC +#define IO_CTRL_SPICLK_INDEX 0x00000037 +#define IO_CTRL_SPICLK_RESET 0x00000318 + +static inline void io_ctrl_spiclk_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_SPICLK_ADDR, value); +} + +/* + * @brief FWR_EN_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FWR_EN_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000F0) +#define IO_CTRL_FWR_EN_1_OFFSET 0x000000F0 +#define IO_CTRL_FWR_EN_1_INDEX 0x0000003C +#define IO_CTRL_FWR_EN_1_RESET 0x00000318 + +static inline void io_ctrl_fwr_en_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FWR_EN_1_ADDR, value); +} + +/* + * @brief FASTWR_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000F8) +#define IO_CTRL_FASTWR_7_OFFSET 0x000000F8 +#define IO_CTRL_FASTWR_7_INDEX 0x0000003E +#define IO_CTRL_FASTWR_7_RESET 0x00000318 + +static inline void io_ctrl_fastwr_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_7_ADDR, value); +} + +/* + * @brief FASTWR_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000FC) +#define IO_CTRL_FASTWR_6_OFFSET 0x000000FC +#define IO_CTRL_FASTWR_6_INDEX 0x0000003F +#define IO_CTRL_FASTWR_6_RESET 0x00000318 + +static inline void io_ctrl_fastwr_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_6_ADDR, value); +} + +/* + * @brief FASTWR_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000100) +#define IO_CTRL_FASTWR_5_OFFSET 0x00000100 +#define IO_CTRL_FASTWR_5_INDEX 0x00000040 +#define IO_CTRL_FASTWR_5_RESET 0x00000318 + +static inline void io_ctrl_fastwr_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_5_ADDR, value); +} + +/* + * @brief FASTWR_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000104) +#define IO_CTRL_FASTWR_4_OFFSET 0x00000104 +#define IO_CTRL_FASTWR_4_INDEX 0x00000041 +#define IO_CTRL_FASTWR_4_RESET 0x00000318 + +static inline void io_ctrl_fastwr_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_4_ADDR, value); +} + +/* + * @brief FASTWR_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000108) +#define IO_CTRL_FASTWR_3_OFFSET 0x00000108 +#define IO_CTRL_FASTWR_3_INDEX 0x00000042 +#define IO_CTRL_FASTWR_3_RESET 0x00000318 + +static inline void io_ctrl_fastwr_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_3_ADDR, value); +} + +/* + * @brief FASTWR_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000010C) +#define IO_CTRL_FASTWR_2_OFFSET 0x0000010C +#define IO_CTRL_FASTWR_2_INDEX 0x00000043 +#define IO_CTRL_FASTWR_2_RESET 0x00000318 + +static inline void io_ctrl_fastwr_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_2_ADDR, value); +} + +/* + * @brief FASTWR_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000110) +#define IO_CTRL_FASTWR_1_OFFSET 0x00000110 +#define IO_CTRL_FASTWR_1_INDEX 0x00000044 +#define IO_CTRL_FASTWR_1_RESET 0x00000318 + +static inline void io_ctrl_fastwr_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_1_ADDR, value); +} + + +/* + * @brief FASTWR_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000114) +#define IO_CTRL_FASTWR_0_OFFSET 0x00000114 +#define IO_CTRL_FASTWR_0_INDEX 0x00000045 +#define IO_CTRL_FASTWR_0_RESET 0x00000318 + +static inline void io_ctrl_fastwr_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_0_ADDR, value); +} + +#endif /* CL_REG_IO_CTRL_H */