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Mon, 13 Jan 2025 03:23:59 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:23:58 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block Date: Mon, 13 Jan 2025 11:23:44 +0000 Message-ID: <20250113112349.801875-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. For example, specific bits in these registers indicate resets caused by events such as underflow or overflow of the watchdog timer. This functionality allows the watchdog driver to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block, allowing drivers to interact with the CPG_ERROR_RSTm registers as required. Signed-off-by: Lad Prabhakar --- Note, there is no ABI breakage as, this series adds the first `syscon` user and also note the driver doesnt fail if the `syscon` property isnt present in the cpg node to handle backward compatibility. --- v2->v3 - No change v1->v2 - No change --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f42d79e73e70 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -17,9 +17,11 @@ description: properties: compatible: - enum: - - renesas,r9a09g047-cpg # RZ/G3E - - renesas,r9a09g057-cpg # RZ/V2H + items: + - enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H + - const: syscon reg: maxItems: 1 @@ -73,7 +75,7 @@ additionalProperties: false examples: - | clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0x10420000 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal";