From patchwork Wed Oct 26 06:33:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Runyang Chen X-Patchwork-Id: 619159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD6BBFA373D for ; Wed, 26 Oct 2022 06:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229995AbiJZGd7 (ORCPT ); Wed, 26 Oct 2022 02:33:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233212AbiJZGdx (ORCPT ); Wed, 26 Oct 2022 02:33:53 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83C2EA98E5; Tue, 25 Oct 2022 23:33:45 -0700 (PDT) X-UUID: cca4552d14ad486bb6c4e637fca7acfe-20221026 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=E9hEc2Vpt24N4yt2JJ2UCDYftPyEeRKVhboZSuZeuhM=; b=JfNcQeWHdmzij3jFxMLw45TY2hFAvj0SLKp7iwD9z8v7W0LLedzI9SUNKHjUxR1eoP/1r6l+icoprzkZhIr9DiWPWLYP+e6lLoUdL7NfFWaF/9l1PPwgXTXiC45lOaTiO7tcOOdoREZY5u2SkxF0DVk0JiMkGxnHR2ZpKh1/hTc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12, REQID:5f8dd05a-e328-4c83-b704-16ae07001633, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327, CLOUDID:541b2b27-9eb1-469f-b210-e32d06cfa36e, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: cca4552d14ad486bb6c4e637fca7acfe-20221026 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 745900504; Wed, 26 Oct 2022 14:33:40 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 26 Oct 2022 14:33:38 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 26 Oct 2022 14:33:37 +0800 From: Runyang Chen To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , "Matthias Brugger" , Rob Herring , "Philipp Zabel" , CC: , , , , , , , Runyang Chen Subject: [RESEND v3 2/3] dt-bindings: reset: mt8188: add toprgu reset-controller header file Date: Wed, 26 Oct 2022 14:33:26 +0800 Message-ID: <20221026063327.20037-3-Runyang.Chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20221026063327.20037-1-Runyang.Chen@mediatek.com> References: <20221026063327.20037-1-Runyang.Chen@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org From: Runyang Chen Add toprgu reset-controller header file for MT8188 Signed-off-by: Runyang Chen Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Guenter Roeck --- include/dt-bindings/reset/mt8188-resets.h | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/dt-bindings/reset/mt8188-resets.h diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h new file mode 100644 index 000000000000..377cdfda82a9 --- /dev/null +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Runyang Chen + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8188 + +#define MT8188_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8188_TOPRGU_IPU0_SW_RST 2 +#define MT8188_TOPRGU_IPU1_SW_RST 3 +#define MT8188_TOPRGU_IPU2_SW_RST 4 +#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 +#define MT8188_TOPRGU_INFRA_SW_RST 6 +#define MT8188_TOPRGU_MMSYS_SW_RST 7 +#define MT8188_TOPRGU_MFG_SW_RST 8 +#define MT8188_TOPRGU_VENC_SW_RST 9 +#define MT8188_TOPRGU_VDEC_SW_RST 10 +#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 +#define MT8188_TOPRGU_SCP_SW_RST 12 +#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8188_TOPRGU_AUDIO_SW_RST 14 +#define MT8188_TOPRGU_CAMSYS_SW_RST 15 +#define MT8188_TOPRGU_MJC_SW_RST 16 +#define MT8188_TOPRGU_PERI_SW_RST 17 +#define MT8188_TOPRGU_PERI_AO_SW_RST 18 +#define MT8188_TOPRGU_PCIE_SW_RST 19 +#define MT8188_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8188_TOPRGU_DPTX_SW_RST 22 +#define MT8188_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8188_TOPRGU_SW_RST_NUM 24 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */