| Message ID | 20220119230626.31560-1-terry.bowman@amd.com |
|---|---|
| Headers | show |
| Series | i2c: piix4: Replace cd6h/cd7h port I/O accesses with MMIO accesses | expand |
On Thu, Jan 20, 2022 at 1:06 AM Terry Bowman <terry.bowman@amd.com> wrote: > > This series changes the piix4_smbus driver's cd6h/cd7h port I/O accesses > to use MMIO instead. This is necessary because cd6h/cd7h port I/O may be > disabled on later AMD processors. > > This series includes patches with MMIO accesses to registers > FCH::PM::DECODEEN and FCH::PM::ISACONTROL. The same registers are also > accessed by the sp5100_tco driver.[1] Synchronization to the MMIO > registers is required in both drivers. > > The first patch creates a macro to request MMIO region using the 'muxed' > retry logic. This is used in patch 6 to synchronize accesses to EFCH MMIO. > > The second patch replaces a hardcoded region size with a #define. This is > to improve maintainability and was requested from v2 review. > > The third patch moves duplicated region request/release code into > functions. This locates related code into functions and reduces code line > count. This will also make adding MMIO support in patch 6 easier. > > The fourth patch moves SMBus controller address detection into a function. > This is in preparation for adding MMIO region support. > > The fifth patch moves EFCH port selection into a function. This is in > preparation for adding MMIO region support. > > The sixth patch adds MMIO support for region requesting/releasing and > mapping. This is necessary for using MMIO to detect SMBus controller > address, enable SMBbus controller region, and control the port select. > > The seventh patch updates the SMBus controller address detection to support > using MMIO. This is necessary because the driver accesses registers > FCH::PM::DECODEEN and FCH::PM::ISACONTOL during initialization and they are > only available using MMIO on later AMD processors. > > The eighth patch updates the SMBus port selection to support MMIO. This is > required because port selection control resides in the > FCH::PM::DECODEEN[smbus0sel] and is only accessible using MMIO on later AMD > processors. > > The ninth patch enables the EFCH MMIO functionality added earlier in this > series. The SMBus controller's PCI revision ID is used to check if EFCH > MMIO is supported by HW and should be enabled in the driver. In general looks good to me, but I believe it will be much better if we agreed on converting driver to use iomap_port() + ioreadXX()/iowriteXX() (means dropping I/O accessor _p variants for good). This would make the series cleaner and less invasive.
This series changes the piix4_smbus driver's cd6h/cd7h port I/O accesses to use MMIO instead. This is necessary because cd6h/cd7h port I/O may be disabled on later AMD processors. This series includes patches with MMIO accesses to registers FCH::PM::DECODEEN and FCH::PM::ISACONTROL. The same registers are also accessed by the sp5100_tco driver.[1] Synchronization to the MMIO registers is required in both drivers. The first patch creates a macro to request MMIO region using the 'muxed' retry logic. This is used in patch 6 to synchronize accesses to EFCH MMIO. The second patch replaces a hardcoded region size with a #define. This is to improve maintainability and was requested from v2 review. The third patch moves duplicated region request/release code into functions. This locates related code into functions and reduces code line count. This will also make adding MMIO support in patch 6 easier. The fourth patch moves SMBus controller address detection into a function. This is in preparation for adding MMIO region support. The fifth patch moves EFCH port selection into a function. This is in preparation for adding MMIO region support. The sixth patch adds MMIO support for region requesting/releasing and mapping. This is necessary for using MMIO to detect SMBus controller address, enable SMBbus controller region, and control the port select. The seventh patch updates the SMBus controller address detection to support using MMIO. This is necessary because the driver accesses registers FCH::PM::DECODEEN and FCH::PM::ISACONTOL during initialization and they are only available using MMIO on later AMD processors. The eighth patch updates the SMBus port selection to support MMIO. This is required because port selection control resides in the FCH::PM::DECODEEN[smbus0sel] and is only accessible using MMIO on later AMD processors. The ninth patch enables the EFCH MMIO functionality added earlier in this series. The SMBus controller's PCI revision ID is used to check if EFCH MMIO is supported by HW and should be enabled in the driver. Based on v5.16. Testing: Tested on family 19h using: i2cdetect -y 0 i2cdetect -y 1 i2cdetect -y 2 - Results using v5.16 and this series applied: # i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: 10 11 -- -- -- -- -- -- 18 -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: 30 -- -- -- -- 35 36 -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- 4a -- -- -- -- -- 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- 73 -- -- -- -- # i2cdetect -y 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: 10 11 -- -- -- -- -- -- 18 -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: 30 -- -- -- -- 35 36 -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- 4a -- -- -- -- -- 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- 73 -- -- -- -- # i2cdetect -y 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- 4c -- -- -- 50: -- 51 -- -- 54 -- -- -- -- -- -- -- -- -- -- -- 60: 60 -- -- 63 -- -- 66 -- -- -- -- 6b -- -- 6e -- 70: 70 71 72 73 74 75 -- 77 - Results using v5.16 (w/o this series applied): # i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- # i2cdetect -y 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- # i2cdetect -y 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Also tested using sp5100_tco submitted series listed below.[1] I applied the sp5100_tco v3 series and ran: cat >> /dev/watchdog [1] sp5100_tco v3 upstream review: Link: https://lore.kernel.org/linux-watchdog/20220118202234.410555-1-terry.bowman@amd.com/ Changes in v3: - Added request_muxed_mem_region() patch (Wolfram, Guenter) - Reduced To/Cc list length. (Andy) Changes in v2: - Split single patch. (Jean Delvare) - Replace constant 2 with SB800_PIIX4_SMB_MAP_SIZE where appropriate. (Jean Delvare) - Shorten SB800_PIIX4_FCH_PM_DECODEEN_MMIO_EN name length to SB800_PIIX4_FCH_PM_DECODEEN_MMIO. (Jean Delvare) - Change AMD_PCI_SMBUS_REVISION_MMIO from 0x59 to 0x51. (Terry Bowman) - Change piix4_sb800_region_setup() to piix4_sb800_region_request(). (Jean Delvare) - Change 'SMB' text in logging to 'SMBus' (Jean Delvare) - Remove unnecessary NULL assignment in piix4_sb800_region_release(). (Jean Delvare) - Move 'u8' variable definitions to single line. (Jean Delvare) - Hardcode piix4_setup_sb800_smba() return value to 0 since it is always 0. (Jean Delvare) Terry Bowman (9): kernel/resource: Introduce request_muxed_mem_region() i2c: piix4: Replace hardcoded memory map size with a #define i2c: piix4: Move port I/O region request/release code into functions i2c: piix4: Move SMBus controller base address detect into function i2c: piix4: Move SMBus port selection into function i2c: piix4: Add EFCH MMIO support to region request and release i2c: piix4: Add EFCH MMIO support to SMBus base address detect i2c: piix4: Add EFCH MMIO support for SMBus port select i2c: piix4: Enable EFCH MMIO for Family 17h+ drivers/i2c/busses/i2c-piix4.c | 208 ++++++++++++++++++++++++++------- include/linux/ioport.h | 2 + 2 files changed, 165 insertions(+), 45 deletions(-)