From patchwork Thu Jan 14 02:53:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thinh Nguyen X-Patchwork-Id: 363308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60447C433E0 for ; Thu, 14 Jan 2021 02:54:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F23623602 for ; Thu, 14 Jan 2021 02:54:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727383AbhANCyr (ORCPT ); Wed, 13 Jan 2021 21:54:47 -0500 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:54756 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726903AbhANCyq (ORCPT ); Wed, 13 Jan 2021 21:54:46 -0500 Received: from mailhost.synopsys.com (sv2-mailhost2.synopsys.com [10.205.2.134]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 3EFBDC00E8; Thu, 14 Jan 2021 02:53:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1610592826; bh=pG5HGJ4CA0OpJ9fui3M+QSjNOMdND+1UCPEDmGQ8M/I=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=hcjxBTU4IndW7MTNz56bhgaGqajD9+3Rz/cJ1QHoLUTi0xLwdW47vryRoaHo6I3ZB iizT5JuZ6U+Td2wqrSbLf2pX79mjfRUmFUpiaEDjQfOB7oOEsnAStqA5aZW7rIaHKg NS0DuHXIHNtovWMd9qHy3X0MSxkl+8D6vmGslHx1ZU/kwgUbUv6XjIxckH3hbYYphd EOaJzuERWnmEBdgdcLCnGzkEpDoaXDWzxeuKYFLUKdy3IA+58/CTs23hR+tWgHXAoW Cjq7oSwHCsl//ykGDXk1FpEedo1/Q0wX4/6fEmVE+LE7SYXtGJm9544fop9SUCuIrr 8GNHiOgnqjynQ== Received: from te-lab16 (unknown [10.10.52.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 10AA0A0096; Thu, 14 Jan 2021 02:53:45 +0000 (UTC) Received: by te-lab16 (sSMTP sendmail emulation); Wed, 13 Jan 2021 18:53:45 -0800 Date: Wed, 13 Jan 2021 18:53:45 -0800 Message-Id: In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Thinh Nguyen Subject: [PATCH v6 10/11] usb: dwc3: gadget: Track connected SSP rate and lane count To: Felipe Balbi , Greg Kroah-Hartman , Thinh.Nguyen@synopsys.com, linux-usb@vger.kernel.org Cc: John Youn Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Track the number of connected lanes and speed in corresponding enum usb_ssp_rate for SuperSpeed Plus capable device. Signed-off-by: Thinh Nguyen --- Changes in v6: - Rebase on Greg's usb-testing branch - Update commmit message - Update to report the rate and lane count in usb_ssp_rate enum Changes in v5: - Rebase on Felipe's testing/next branch - Changed Signed-off-by email to match From: email header Changes in v4: - None Changes in v3: - Update commit with updated field name - No longer use DWC3_LSM_5/10_GBPS macros Changes in v2: - Fix missing check for gen1x2 when writing to sublink speed attributes - Minor fix in commit message (first commit sentence ended with comma) drivers/usb/dwc3/core.h | 2 ++ drivers/usb/dwc3/gadget.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 8f6e71052c6c..304912e84053 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -461,6 +461,8 @@ #define DWC3_DEVTEN_USBRSTEN BIT(1) #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) +#define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ + /* Device Status Register */ #define DWC3_DSTS_DCNRD BIT(29) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 7f06baac8b62..f46498f6d794 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2120,6 +2120,12 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc) reg |= DWC3_DCFG_SUPERSPEED_PLUS; } } + + if (DWC3_IP_IS(DWC32) && + dwc->gadget_max_speed > USB_SPEED_UNKNOWN && + dwc->gadget_max_speed < USB_SPEED_SUPER_PLUS) + reg &= ~DWC3_DCFG_NUMLANES(~0); + dwc3_writel(dwc->regs, DWC3_DCFG, reg); } @@ -3370,12 +3376,18 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) struct dwc3_ep *dep; int ret; u32 reg; + u8 lanes = 1; u8 speed; reg = dwc3_readl(dwc->regs, DWC3_DSTS); speed = reg & DWC3_DSTS_CONNECTSPD; dwc->speed = speed; + if (DWC3_IP_IS(DWC32)) + lanes = DWC3_DSTS_CONNLANES(reg) + 1; + + dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; + /* * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed * each time on Connect Done. @@ -3390,6 +3402,11 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); dwc->gadget->ep0->maxpacket = 512; dwc->gadget->speed = USB_SPEED_SUPER_PLUS; + + if (lanes > 1) + dwc->gadget->ssp_rate = USB_SSP_GEN_2x2; + else + dwc->gadget->ssp_rate = USB_SSP_GEN_2x1; break; case DWC3_DSTS_SUPERSPEED: /* @@ -3411,6 +3428,11 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); dwc->gadget->ep0->maxpacket = 512; dwc->gadget->speed = USB_SPEED_SUPER; + + if (lanes > 1) { + dwc->gadget->speed = USB_SPEED_SUPER_PLUS; + dwc->gadget->ssp_rate = USB_SSP_GEN_1x2; + } break; case DWC3_DSTS_HIGHSPEED: dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); @@ -3905,6 +3927,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) dev->platform_data = dwc; dwc->gadget->ops = &dwc3_gadget_ops; dwc->gadget->speed = USB_SPEED_UNKNOWN; + dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; dwc->gadget->sg_supported = true; dwc->gadget->name = "dwc3-gadget"; dwc->gadget->lpm_capable = true;