@@ -367,12 +367,12 @@ int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
return -EINVAL;
/* IMODI value in IMOD register is in 250ns increments */
- imod_interval = umin(imod_interval / 250, ER_IRQ_INTERVAL_MASK);
+ imod_interval = umin(imod_interval / 250, IMODI_MASK);
- imod = readl(&ir->ir_set->irq_control);
- imod &= ~ER_IRQ_INTERVAL_MASK;
+ imod = readl(&ir->ir_set->imod);
+ imod &= ~IMODI_MASK;
imod |= imod_interval;
- writel(imod, &ir->ir_set->irq_control);
+ writel(imod, &ir->ir_set->imod);
return 0;
}
@@ -835,7 +835,7 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
ir->s3_iman = readl(&ir->ir_set->iman);
- ir->s3_irq_control = readl(&ir->ir_set->irq_control);
+ ir->s3_imod = readl(&ir->ir_set->imod);
}
}
@@ -859,7 +859,7 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
writel(ir->s3_iman, &ir->ir_set->iman);
- writel(ir->s3_irq_control, &ir->ir_set->irq_control);
+ writel(ir->s3_imod, &ir->ir_set->imod);
}
}
@@ -213,7 +213,7 @@ struct xhci_op_regs {
* struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2.
* @iman: IMAN - Interrupt Management Register. Used to enable
* interrupts and check for pending interrupts.
- * @irq_control: IMOD - Interrupt Moderation Register. Used to throttle interrupts.
+ * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts.
* @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST).
* @erst_base: ERSTBA - Event ring segment table base address.
* @erst_dequeue: ERDP - Event ring dequeue pointer.
@@ -227,7 +227,7 @@ struct xhci_op_regs {
*/
struct xhci_intr_reg {
__le32 iman;
- __le32 irq_control;
+ __le32 imod;
__le32 erst_size;
__le32 rsvd;
__le64 erst_base;
@@ -240,15 +240,15 @@ struct xhci_intr_reg {
/* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */
#define IMAN_IE (1 << 1)
-/* irq_control bitmasks */
+/* imod bitmasks */
/*
* bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts
* (in 250ns intervals). The interval between interrupts will be longer if there are no
* events on the event ring. Default is 4000 (1 ms).
*/
-#define ER_IRQ_INTERVAL_MASK (0xffff)
+#define IMODI_MASK (0xffff)
/* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */
-#define ER_IRQ_COUNTER_MASK (0xffff << 16)
+#define IMODC_MASK (0xffff << 16)
/* erst_size bitmasks */
/* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */
@@ -1453,7 +1453,7 @@ struct xhci_interrupter {
u32 isoc_bei_interval;
/* For interrupter registers save and restore over suspend/resume */
u32 s3_iman;
- u32 s3_irq_control;
+ u32 s3_imod;
u32 s3_erst_size;
u64 s3_erst_base;
u64 s3_erst_dequeue;