From patchwork Sat Oct 5 19:27:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 833206 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F0716190B; Sat, 5 Oct 2024 19:30:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728156640; cv=none; b=h7cMFAB58jCk5QMWxVGvrjS964zfCGhmUb7e1W+dC/UhS2rN81ooJMPyEe41+2C4uKMaBJjwG0pfs6TF5bzoxf/y3QqoHxpJBa/eA0VYxR7I9pqo1qpsmTDdUcAAMH+A4kO3VAFcq/vP4toV4058AK+ZRNNZEtVDyROu0k0TXhQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728156640; c=relaxed/simple; bh=3AiGtnG75PKSTtiH979M1yZh3PT8uAdBaY7xcXMoDm0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EntQTQxe1pHu7oP1RxT4A8YHdXtSMKQB4kSHP45A085WlPudo3rSbSEdAvkpPpFrFOLmwZH8lHz9SPTBuSvWv5UfcwXmk5ZuMXDsErFnheMZx7j26rBbRYP4JXpvKc609uXKCk2g+Z3u56d2+Rp3Lpu8AW1g3Bw4LA0lA9DBTJ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Iov8dH2d; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Iov8dH2d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728156639; x=1759692639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3AiGtnG75PKSTtiH979M1yZh3PT8uAdBaY7xcXMoDm0=; b=Iov8dH2dwyEUQmMRvl5g6dOi7BIJNP3D2hfwXGvOm+YDtsyFwILmEjA8 q1wAlwN5IwD0NAl29oAsGWQC/cYlTHIeW4cQyxd58K5Bha241AWgrNr6W Sxh97ZUVm3Kw5dMKPmOF0BsPevArncwpC7nyvPBJXMLUR/qTqKGYbyL5+ r1ZypsHtv25LvtNcU/3psA+ZQr4IIj+YYPaG5wqkOx2rGQ3fZ8oM4ugPr IjTRcZsLK5VHIQBSyXUuhHReML1xoXoNNVrjMlPHhoDzf5iWiVyOEVkpN XI3gVVM5NvZWwLA5Y0OEBXeRdJoSIrI21GXS++y1o93EAYbMTun6QJD1w w==; X-CSE-ConnectionGUID: UgSOsKraTneXkJ6U1c+USw== X-CSE-MsgGUID: 3FZWcdFTTKOlNcVDMRNJ2g== X-IronPort-AV: E=McAfee;i="6700,10204,11216"; a="44879470" X-IronPort-AV: E=Sophos;i="6.11,181,1725346800"; d="scan'208";a="44879470" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2024 12:30:36 -0700 X-CSE-ConnectionGUID: 44lp5oojT8qwM1ceYeU8nw== X-CSE-MsgGUID: C8x2XNQrRGOgOMeZTFCFUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,181,1725346800"; d="scan'208";a="74861626" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa010.jf.intel.com with ESMTP; 05 Oct 2024 12:30:33 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 0B12A4BB; Sat, 05 Oct 2024 22:30:32 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-usb@vger.kernel.org Cc: Andy Shevchenko , Lee Jones , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Heikki Krogerus , Greg Kroah-Hartman , Zhang Ning Subject: [PATCH v2 3/4] mfd: intel_soc_pmic_bxtwc: Use IRQ domain for PMIC devices Date: Sat, 5 Oct 2024 22:27:06 +0300 Message-ID: <20241005193029.1929139-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20241005193029.1929139-1-andriy.shevchenko@linux.intel.com> References: <20241005193029.1929139-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 While design wise the idea of converting the driver to use the hierarchy of the IRQ chips is correct, the implementation has (inherited) flaws. This was unveiled when platform_get_irq() had started WARN() on IRQ 0 that is supposed to be a Linux IRQ number (also known as vIRQ). Rework the driver to respect IRQ domain when creating each MFD device separately, as the domain is not the same for all of them. Fixes: 57129044f504 ("mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips") Tested-by: Zhang Ning Signed-off-by: Andy Shevchenko --- drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +++++++++++++++++------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c index 628108dcf545..fefbeb4164fd 100644 --- a/drivers/mfd/intel_soc_pmic_bxtwc.c +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c @@ -230,21 +230,11 @@ static const struct resource tmu_resources[] = { }; static struct mfd_cell bxt_wc_dev[] = { - { - .name = "bxt_wcove_gpadc", - .num_resources = ARRAY_SIZE(adc_resources), - .resources = adc_resources, - }, { .name = "bxt_wcove_thermal", .num_resources = ARRAY_SIZE(thermal_resources), .resources = thermal_resources, }, - { - .name = "bxt_wcove_bcu", - .num_resources = ARRAY_SIZE(bcu_resources), - .resources = bcu_resources, - }, { .name = "bxt_wcove_gpio", .num_resources = ARRAY_SIZE(gpio_resources), @@ -263,6 +253,22 @@ static const struct mfd_cell bxt_wc_tmu_dev[] = { }, }; +static const struct mfd_cell bxt_wc_bcu_dev[] = { + { + .name = "bxt_wcove_bcu", + .num_resources = ARRAY_SIZE(bcu_resources), + .resources = bcu_resources, + }, +}; + +static const struct mfd_cell bxt_wc_adc_dev[] = { + { + .name = "bxt_wcove_gpadc", + .num_resources = ARRAY_SIZE(adc_resources), + .resources = adc_resources, + }, +}; + static struct mfd_cell bxt_wc_chgr_dev[] = { { .name = "bxt_wcove_usbc", @@ -508,23 +514,23 @@ static int bxtwc_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n"); - /* Add chained IRQ handler for BCU IRQs */ - ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, - BXTWC_BCU_LVL1_IRQ, - IRQF_ONESHOT, - &bxtwc_regmap_irq_chip_bcu, - &pmic->irq_chip_data_bcu); + ret = bxtwc_add_chained_devices(pmic, bxt_wc_bcu_dev, ARRAY_SIZE(bxt_wc_bcu_dev), + pmic->irq_chip_data, + BXTWC_BCU_LVL1_IRQ, + IRQF_ONESHOT, + &bxtwc_regmap_irq_chip_bcu, + &pmic->irq_chip_data_bcu); if (ret) - return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n"); + return ret; - /* Add chained IRQ handler for ADC IRQs */ - ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, - BXTWC_ADC_LVL1_IRQ, - IRQF_ONESHOT, - &bxtwc_regmap_irq_chip_adc, - &pmic->irq_chip_data_adc); + ret = bxtwc_add_chained_devices(pmic, bxt_wc_adc_dev, ARRAY_SIZE(bxt_wc_adc_dev), + pmic->irq_chip_data, + BXTWC_ADC_LVL1_IRQ, + IRQF_ONESHOT, + &bxtwc_regmap_irq_chip_adc, + &pmic->irq_chip_data_adc); if (ret) - return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n"); + return ret; ret = bxtwc_add_chained_devices(pmic, bxt_wc_chgr_dev, ARRAY_SIZE(bxt_wc_chgr_dev), pmic->irq_chip_data,