From patchwork Thu Aug 29 09:45:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faisal Hassan X-Patchwork-Id: 823956 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A70B7189F37; Thu, 29 Aug 2024 09:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724924739; cv=none; b=bC6QAi2Bdnxaq/8r+zeskpH0rf/lCo3kE7V6AG/+z9WmE2HNDXDg3FsqHG2hkXtd4OapvhP15SoreYDzbakKWUKXFmcxegj27lyY52BOyJkE+sB12hZkEFvhIrfgRsz77Aqhl8+gt0H2HGwcvXLPZ7AYeLtuandss88L7BLydAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724924739; c=relaxed/simple; bh=4ueHelHgSTqT3lKO+PyUF90mHm7gbgnOAxqWdSm+Ulg=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=jx6oquAW3n8ibTdns8ZllMjf4LU+JMxyr9vb7JmzFGySRvlhBaX5pXSfkPSE5OiL+s/CIZQf88rDIuh7OsUbRfCCvg4SVABL3ySX6y5u51JjqQSMFnq5X7nckrDwH5Y4UXLYSZ/ir8S/cju/WY5/g8nawRf5uAIqYb81SMnZ3u0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jTZ1aBJr; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jTZ1aBJr" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47T8Pba2014958; Thu, 29 Aug 2024 09:45:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:message-id:mime-version:subject:to; s= qcppdkim1; bh=jNegF+g1xhVssgmkjuQ/vzvKlzG4fD1d4RD6qVQLKtk=; b=jT Z1aBJrAkXn5hp02TIr1+g/9Elg7hCL/9jvBFUk2kkhQKVLg5k5dLDTdbI0CXFou6 up6rrPHuGZoazj7dPd8o3pCu+u74PLF8M1/t6uwCZ3o8AcXhxu9dOnWZ1SJ9iw5k o1hed4CHRpYkUy8QygwGqvz9BcfdNumD3jf9//07Bf7tho09NYq8iCfAC3ovUgGH uU65tgPeIIbrNXnHIrBaBRoegBxthZKk47sgrQz338HxxZNjFasogI8r4Evp2ATg rtscAKjJB1UilnCPxg3T5P4QHjABstrMpsa/XMbo0BQH2yrupSDkQhdMijN+0z8g SUoGjNYCsvwYNupOVXpg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419px5mp1b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 09:45:32 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47T9jFrk020098 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 09:45:15 GMT Received: from hu-faisalh-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 02:45:13 -0700 From: Faisal Hassan To: Thinh Nguyen , Greg Kroah-Hartman CC: , , Faisal Hassan , Subject: [PATCH v2] usb: dwc3: core: update LC timer as per USB Spec V3.2 Date: Thu, 29 Aug 2024 15:15:02 +0530 Message-ID: <20240829094502.26502-1-quic_faisalh@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FauzJH8HQ6X88T0VtEzu_JSg2OyxzIQC X-Proofpoint-GUID: FauzJH8HQ6X88T0VtEzu_JSg2OyxzIQC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_02,2024-08-29_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290072 This fix addresses STAR 9001285599, which only affects DWC_usb3 version 3.20a. The timer value for PM_LC_TIMER in DWC_usb3 3.20a for the Link ECN changes is incorrect. If the PM TIMER ECN is enabled via GUCTL2[19], the link compliance test (TD7.21) may fail. If the ECN is not enabled (GUCTL2[19] = 0), the controller will use the old timer value (5us), which is still acceptable for the link compliance test. Therefore, clear GUCTL2[19] to pass the USB link compliance test: TD 7.21. Cc: stable@vger.kernel.org Signed-off-by: Faisal Hassan Acked-by: Thinh Nguyen --- Changes in v2: Updated comment and commit message to include the controller IP. v1 link: https://lore.kernel.org/all/20240822084504.1355-1-quic_faisalh@quicinc.com drivers/usb/dwc3/core.c | 15 +++++++++++++++ drivers/usb/dwc3/core.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 734de2a8bd21..92d7ec830322 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1378,6 +1378,21 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } + /* + * STAR 9001285599: This issue affects DWC_usb3 version 3.20a + * only. If the PM TIMER ECM is enabled through GUCTL2[19], the + * link compliance test (TD7.21) may fail. If the ECN is not + * enabled (GUCTL2[19] = 0), the controller will use the old timer + * value (5us), which is still acceptable for the link compliance + * test. Therefore, do not enable PM TIMER ECM in 3.20a by + * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0. + */ + if (DWC3_VER_IS(DWC3, 320A)) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); + reg &= ~DWC3_GUCTL2_LC_TIMER; + dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); + } + /* * When configured in HOST mode, after issuing U3/L2 exit controller * fails to send proper CRC checksum in CRC5 feild. Because of this diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 1e561fd8b86e..c71240e8f7c7 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -421,6 +421,7 @@ /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) +#define DWC3_GUCTL2_LC_TIMER BIT(19) /* Global User Control Register 3 */ #define DWC3_GUCTL3_SPLITDISABLE BIT(14) @@ -1269,6 +1270,7 @@ struct dwc3 { #define DWC3_REVISION_290A 0x5533290a #define DWC3_REVISION_300A 0x5533300a #define DWC3_REVISION_310A 0x5533310a +#define DWC3_REVISION_320A 0x5533320a #define DWC3_REVISION_330A 0x5533330a #define DWC31_REVISION_ANY 0x0