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[34.125.73.210]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-7127add7660sm7040294b3a.38.2024.08.19.15.39.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2024 15:39:11 -0700 (PDT) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, devicetree@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Andrzej Hajda , Benson Leung , Conor Dooley , Daniel Vetter , David Airlie , Dmitry Baryshkov , dri-devel@lists.freedesktop.org, Guenter Roeck , Jernej Skrabec , Jonas Karlman , Krzysztof Kozlowski , Laurent Pinchart , Lee Jones , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Prashant Malani , Robert Foss , Rob Herring , Thomas Zimmermann , Tzung-Bi Shih , Alexandre Belloni , Andy Shevchenko , Daniel Scally , Greg Kroah-Hartman , Heikki Krogerus , Ivan Orlov , linux-acpi@vger.kernel.org, linux-usb@vger.kernel.org, Mika Westerberg , "Rafael J . Wysocki" , Sakari Ailus , Vinod Koul Subject: [PATCH v3 16/17] platform/chrome: cros_ec_typec: Support DP muxing Date: Mon, 19 Aug 2024 15:38:30 -0700 Message-ID: <20240819223834.2049862-17-swboyd@chromium.org> X-Mailer: git-send-email 2.46.0.184.g6999bdac58-goog In-Reply-To: <20240819223834.2049862-1-swboyd@chromium.org> References: <20240819223834.2049862-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Most ARM based chromebooks with two usb-c-connector nodes and one DP controller are muxing the DP lanes between the two USB ports. This is done so that the type-c ports are at least equal in capability if not functionality. Either an analog mux is used to steer the DP signal to one or the other port, or a DP bridge chip has two lanes (e.g. DP ML0/ML1) wired to one type-c port while the other two (e.g. DP ML2/ML3) are wired to another type-c port. Implement the same algorithm that the EC has to figure out which type-c port has actually been muxed for DP altmode. Wait for the first type-c port to assert HPD, and treat that as the actively muxed port until the port exits DP altmode entirely. Allow HPD to be asserted or deasserted during this time. If the port isn't active, simply ignore those events and skip calling cros_typec_enable_dp(). Otherwise, pass the DP information to the typec subsystem so that the DP controller can respond to HPD events and pin configurations. The EC can mux the DP signal to any number of USB type-c ports. We only need to make sure that the active USB type-c port is tracked so that DP information about the other ports is ignored. Unfortunately, the EC doesn't hide these details from the AP so we have to reimplement the logic in the kernel. Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_ec_typec.c | 27 +++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index f7e184fa90c5..b32abd14825c 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -27,6 +27,7 @@ struct cros_typec_dp_bridge { struct cros_typec_data *typec_data; struct drm_dp_typec_bridge_dev *dev; + struct cros_typec_port *active_port; }; #define DP_PORT_VDO (DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASSIGN_D)) | \ @@ -651,6 +652,7 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, struct ec_response_usb_pd_control_v2 *pd_ctrl) { struct cros_typec_port *port = typec->ports[port_num]; + struct cros_typec_dp_bridge *dp_bridge = typec->dp_bridge; struct ec_response_usb_pd_mux_info resp; struct ec_params_usb_pd_mux_info req = { .port = port_num, @@ -658,6 +660,7 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, struct ec_params_usb_pd_mux_ack mux_ack; enum typec_orientation orientation; int ret; + bool dp_enabled, hpd_asserted, is_active_port; ret = cros_ec_cmd(typec->ec, 0, EC_CMD_USB_PD_MUX_INFO, &req, sizeof(req), &resp, sizeof(resp)); @@ -671,6 +674,20 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, if (port->mux_flags == resp.flags && port->role == pd_ctrl->role) return 0; + dp_enabled = resp.flags & USB_PD_MUX_DP_ENABLED; + hpd_asserted = resp.flags & USB_PD_MUX_HPD_LVL; + /* + * Assume the first port to have HPD asserted is the one muxed to DP + * (i.e. active_port). When there's only one port this delays setting + * the active_port until HPD is asserted, but before that the + * drm_connector looks disconnected so active_port doesn't need to be + * set. + */ + if (dp_bridge && hpd_asserted && !dp_bridge->active_port) + dp_bridge->active_port = port; + + is_active_port = !dp_bridge || dp_bridge->active_port == port; + port->mux_flags = resp.flags; port->role = pd_ctrl->role; @@ -698,8 +715,11 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, ret = cros_typec_enable_usb4(typec, port_num, pd_ctrl); } else if (port->mux_flags & USB_PD_MUX_TBT_COMPAT_ENABLED) { ret = cros_typec_enable_tbt(typec, port_num, pd_ctrl); - } else if (port->mux_flags & USB_PD_MUX_DP_ENABLED) { - ret = cros_typec_enable_dp(typec, port_num, pd_ctrl); + } else if (dp_enabled) { + ret = 0; + /* Ignore DP events for the non-active port */ + if (is_active_port) + ret = cros_typec_enable_dp(typec, port_num, pd_ctrl); } else if (port->mux_flags & USB_PD_MUX_SAFE_MODE) { ret = cros_typec_usb_safe_state(port); } else if (port->mux_flags & USB_PD_MUX_USB_ENABLED) { @@ -716,6 +736,9 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, } mux_ack: + if (dp_bridge && !dp_enabled && is_active_port) + dp_bridge->active_port = NULL; + if (!typec->needs_mux_ack) return ret;