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AJvYcCXWN242Jkp2grSF5VbL1+1kALq8yfCGwuKKWcb3w0wxlAUi8NnRNQcBonYuGGMQMPb4ccoKmwptr0No3F6v9ia+z/nNh0UEU01n/RtG6mQvDE+0HR2ZcHR4zsglEGpi29TnOnJEhu/Em6jmopRIq6H+JJz+UVKl5zijqBhC4nSGR5kijiCLHv6YQkBsZ+pIkZR5ntSRwSIhf9QufOgYENsGx0S8Nsh2a2denFFhMjiifIbwNvF49k8yBlmndAS+xAxg X-Gm-Message-State: AOJu0YzymXyavR0N6ve+eUtYASxulxA+o2fgdjKyghvJ6kqijvHVMcIO s17ahDnDj1j3GN+otVHjKwQyplDShhkXiuUN6EtA55JlDaxit5qM X-Google-Smtp-Source: AGHT+IGa5nC1Rod9C1LgjK7SeiNLsR+u3R/s3yoxrcJTPD4mCFyFTsvxjXR/YMhGhKGnpQz0KnmiGQ== X-Received: by 2002:a17:906:fe0c:b0:a77:cf9d:f495 with SMTP id a640c23a62f3a-a7dc508d3e0mr701470466b.40.1722808543592; Sun, 04 Aug 2024 14:55:43 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:3711:c80:e7a7:e025:f1a5:ef78]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a7dc9d45452sm370485066b.111.2024.08.04.14.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 14:55:43 -0700 (PDT) From: David Virag To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Michael Turquette , Stephen Boyd , Thinh Nguyen , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Sam Protsenko , David Virag , Marek Szyprowski Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 08/13] clk: samsung: clk-pll: Add support for pll_1418x Date: Sun, 4 Aug 2024 23:53:53 +0200 Message-ID: <20240804215458.404085-9-virag.david003@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240804215458.404085-1-virag.david003@gmail.com> References: <20240804215458.404085-1-virag.david003@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pll1418x is used in Exynos7885 SoC for USB PHY clock. Operation-wise it is very similar to pll0822x, except that MDIV is only 9 bits wide instead of 10, and we use the CON1 register in the PLL macro's "con" parameter instead of CON3 like this: PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, pll_usb_rate_table), Technically the PLL should work fine with pll0822x code if the PLL tables are correct, but it's more "correct" to actually update the mask. Signed-off-by: David Virag --- drivers/clk/samsung/clk-pll.c | 20 ++++++++++++++++---- drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 4be879ab917e..c61a2810737c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { #define PLL0822X_LOCK_STAT_SHIFT (29) #define PLL0822X_ENABLE_SHIFT (31) +/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */ +#define PLL1418X_MDIV_MASK (0x1FF) + static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, u64 fvco = parent_rate; pll_con3 = readl_relaxed(pll->con_reg); - mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + if (pll->type != pll_1418x) + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + else + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK; pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; @@ -468,9 +474,14 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, /* Change PLL PMS values */ pll_con3 = readl_relaxed(pll->con_reg); - pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | - (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | - (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); + if (pll->type != pll_1418x) + pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | + (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | + (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); + else + pll_con3 &= ~((PLL1418X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | + (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | + (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | (rate->pdiv << PLL0822X_PDIV_SHIFT) | (rate->sdiv << PLL0822X_SDIV_SHIFT); @@ -1317,6 +1328,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_1418x: case pll_0818x: case pll_0822x: case pll_0516x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index ffd3d52c0dec..1efbe4c446d0 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -30,6 +30,7 @@ enum samsung_pll_type { pll_2650x, pll_2650xx, pll_1417x, + pll_1418x, pll_1450x, pll_1451x, pll_1452x,