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The vendor kernel also stubs out USB3 functions, so we do not support it. It is though, perfectly capable of USB 2.0 high-speed mode, both as host and device. Signed-off-by: David Virag --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 008228fb319a..1352c64d132e 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -463,6 +463,41 @@ i2c_7: i2c@11cd0000 { clock-names = "i2c"; status = "disabled"; }; + + usbdrd: usb@13600000 { + compatible = "samsung,exynos7885-dwusb3"; + ranges = <0x0 0x13600000 0x10000>; + clocks = <&cmu_fsys CLK_FSYS_USB30DRD_BUS_CLK_EARLY>, + <&cmu_fsys CLK_FSYS_USB30DRD_REF_CLK>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + /* + * SoC in theory supports SS but no device has it. + * Actual capabilities unknown. + */ + maximum-speed = "high-speed"; + }; + }; + + usbdrd_phy: phy@135d0000 { + compatible = "samsung,exynos7885-usbdrd-phy"; + reg = <0x135d0000 0x100>; + clocks = <&cmu_fsys CLK_FSYS_USB30DRD_ACLK_20PHYCTRL>, + <&cmu_fsys CLK_FSYS_USB20PHY_CLKCORE>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; }; };