@@ -367,6 +367,7 @@ struct exynos5_usbdrd_phy_drvdata {
int n_clks;
const char * const *core_clk_names;
int n_core_clks;
+ u32 set_ref_clk_rate;
const char * const *regulator_names;
int n_regulators;
u32 pmu_offset_usbdrd0_phy;
@@ -1361,6 +1362,10 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
return dev_err_probe(phy_drd->dev, -ENODEV,
"failed to find phy reference clock\n");
+ /* Exynos7885 SoC has reference clock unset by default */
+ if (phy_drd->drv_data->set_ref_clk_rate)
+ clk_set_rate(ref_clk, phy_drd->drv_data->set_ref_clk_rate);
+
ref_rate = clk_get_rate(ref_clk);
ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
if (ret)
@@ -1460,6 +1465,19 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
};
+static const struct exynos5_usbdrd_phy_drvdata exynos7885_usbdrd_phy = {
+ .phy_cfg = phy_cfg_exynos850,
+ .phy_ops = &exynos850_usbdrd_phy_ops,
+ .pmu_offset_usbdrd0_phy = EXYNOS7885_PHY_CTRL_USB20,
+ .clk_names = exynos5_clk_names,
+ .n_clks = ARRAY_SIZE(exynos5_clk_names),
+ .core_clk_names = exynos5_core_clk_names,
+ .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
+ .regulator_names = exynos5_regulator_names,
+ .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
+ .set_ref_clk_rate = 50 * MHZ,
+};
+
static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos850,
.phy_ops = &exynos850_usbdrd_phy_ops,
@@ -1663,6 +1681,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
}, {
.compatible = "samsung,exynos7-usbdrd-phy",
.data = &exynos7_usbdrd_phy
+ }, {
+ .compatible = "samsung,exynos7885-usbdrd-phy",
+ .data = &exynos7885_usbdrd_phy
}, {
.compatible = "samsung,exynos850-usbdrd-phy",
.data = &exynos850_usbdrd_phy
@@ -657,6 +657,9 @@
#define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268)
#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
+/* For Exynos7885 */
+#define EXYNOS7885_PHY_CTRL_USB20 (0x674)
+
/* For Tensor GS101 */
#define GS101_SYSIP_DAT0 (0x810)
#define GS101_SYSTEM_CONFIGURATION (0x3A00)
The Exynos7885 SoC has an Exynos USB PHY that theoretically supports USB3 SuperSpeed, but all known devices using it only have USB2 and the vendor driver has USB3 function stubbed out, so we'll only support USB2. Apart from this mysterius USB3 capability, it's the closest to Exynos850 out of those supported. Unlike other SoCs though, this one doesn't set the reference clock by default, so we have to set it manually. For this, create a set_ref_clk_rate property in drvdata that can be set to a predefined value to set the clockrate to. Signed-off-by: David Virag <virag.david003@gmail.com> --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 21 +++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 3 +++ 2 files changed, 24 insertions(+)