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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a6dc77dsm146576966b.52.2024.07.10.03.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jul 2024 03:36:25 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 10 Jul 2024 11:36:13 +0100 Subject: [PATCH 06/15] usb: typec: tcpci: use GENMASK() for TCPC_MSG_HDR_INFO_REV Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240710-tcpc-cleanup-v1-6-0ec1f41f4263@linaro.org> References: <20240710-tcpc-cleanup-v1-0-0ec1f41f4263@linaro.org> In-Reply-To: <20240710-tcpc-cleanup-v1-0-0ec1f41f4263@linaro.org> To: Heikki Krogerus , Greg Kroah-Hartman Cc: Peter Griffin , Tudor Ambarus , Will McVicker , Badhri Jagan Sridharan , kernel-team@android.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Draszik?= X-Mailer: b4 0.13.0 Convert field TCPC_MSG_HDR_INFO_REV from register TCPC_MSG_HDR_INFO to using GENMASK() and FIELD_PREP() so as to keep using a similar approach for all fields. Signed-off-by: André Draszik --- drivers/usb/typec/tcpm/tcpci.c | 2 +- include/linux/usb/tcpci.h | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/usb/typec/tcpm/tcpci.c b/drivers/usb/typec/tcpm/tcpci.c index 5ad05a5bbbd1..ad5c9d5bf6a9 100644 --- a/drivers/usb/typec/tcpm/tcpci.c +++ b/drivers/usb/typec/tcpm/tcpci.c @@ -456,7 +456,7 @@ static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached, unsigned int reg; int ret; - reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT; + reg = FIELD_PREP(TCPC_MSG_HDR_INFO_REV, PD_REV20); if (role == TYPEC_SOURCE) reg |= TCPC_MSG_HDR_INFO_PWR_ROLE; if (data == TYPEC_HOST) diff --git a/include/linux/usb/tcpci.h b/include/linux/usb/tcpci.h index 80652d4f722e..3cd61e9f73b3 100644 --- a/include/linux/usb/tcpci.h +++ b/include/linux/usb/tcpci.h @@ -129,9 +129,8 @@ #define TCPC_MSG_HDR_INFO 0x2e #define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) +#define TCPC_MSG_HDR_INFO_REV GENMASK(2, 1) #define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) -#define TCPC_MSG_HDR_INFO_REV_SHIFT 1 -#define TCPC_MSG_HDR_INFO_REV_MASK 0x3 #define TCPC_RX_DETECT 0x2f #define TCPC_RX_DETECT_HARD_RESET BIT(5)