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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D5.mail.protection.outlook.com (10.167.241.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Thu, 13 Jun 2024 05:42:45 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 13 Jun 2024 00:42:43 -0500 From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Greg Kroah-Hartman CC: "open list:PCI SUBSYSTEM" , open list , "open list:USB XHCI DRIVER" , Daniel Drake , Gary Li , Mika Westerberg , "Mario Limonciello" Subject: [PATCH 3/4] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Date: Thu, 13 Jun 2024 00:42:03 -0500 Message-ID: <20240613054204.5850-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613054204.5850-1-mario.limonciello@amd.com> References: <20240613054204.5850-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|DS0PR12MB6392:EE_ X-MS-Office365-Filtering-Correlation-Id: 96c80735-630b-4164-8a53-08dc8b6ba72d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230034)(376008)(1800799018)(82310400020)(36860700007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 05:42:45.8871 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96c80735-630b-4164-8a53-08dc8b6ba72d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6392 As the PCI core now waits for D0 after D3cold exit, the Ryzen XHCI controllers that were quirked to not use D3cold and to add a delay on D3hot no longer need these quirks. Drop both the PCI and XHCI sets of quirks. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 17 ----------------- drivers/usb/host/xhci-pci.c | 11 ----------- drivers/usb/host/xhci.h | 11 +++++------ 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 568410e64ce6..942d0fe12cb1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2059,23 +2059,6 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_nvidia_hda_pm); -/* - * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. - * https://bugzilla.kernel.org/show_bug.cgi?id=205587 - * - * The kernel attempts to transition these devices to D3cold, but that seems - * to be ineffective on the platforms in question; the PCI device appears to - * remain on in D3hot state. The D3hot-to-D0 transition then requires an - * extended delay in order to succeed. - */ -static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) -{ - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); - #ifdef CONFIG_X86_IO_APIC static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) { diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 0614d002aba1..ae330d3df6de 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -314,10 +314,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) xhci->quirks |= XHCI_U2_DISABLE_WAKE; - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) - xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_INTEL_HOST; @@ -743,13 +739,6 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_COMP_MODE_QUIRK) pci_d3cold_disable(pdev); -#ifdef CONFIG_SUSPEND - /* d3cold is broken, but only when s2idle is used */ - if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && - xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) - pci_d3cold_disable(pdev); -#endif - if (xhci->quirks & XHCI_PME_STUCK_QUIRK) xhci_pme_quirk(hcd); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 30415158ed3c..b84b1c48c517 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1621,12 +1621,11 @@ struct xhci_hcd { #define XHCI_DISABLE_SPARSE BIT_ULL(38) #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) #define XHCI_NO_SOFT_RETRY BIT_ULL(40) -#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) -#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) -#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) -#define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) -#define XHCI_ZHAOXIN_HOST BIT_ULL(46) +#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(41) +#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(42) +#define XHCI_RESET_TO_DEFAULT BIT_ULL(43) +#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(44) +#define XHCI_ZHAOXIN_HOST BIT_ULL(45) unsigned int num_active_eps; unsigned int limit_active_eps;