From patchwork Wed Dec 27 06:03:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 758584 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8C8C538D; Wed, 27 Dec 2023 06:03:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LUHhn5xn" X-UUID: a387f432a47d11eea2298b7352fd921d-20231227 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5qBKHfc8i14d6XJhRnuWE5dChDSzj6DCcNgKR3axeCs=; b=LUHhn5xnyJcqn3ecl8vx/aLGhOo4silXeEevSTsZbkbzlQbNk/5i0W4Pmoge3AE1/U1MxSPzaGi4dyxjGnmMb7Lo4ZJVRySTFOiDFBGpqFFoD9d5d/DfqQHSl7u/bBqYXq/nNBcKypprfSjvIkBRXqHqGkWIwsoeG+4NRPcb65g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:2f8e9dfd-0c52-4ce6-9be3-e8a6a89f5620, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:0f499d8d-e2c0-40b0-a8fe-7c7e47299109, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: a387f432a47d11eea2298b7352fd921d-20231227 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1929681496; Wed, 27 Dec 2023 14:03:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 27 Dec 2023 14:03:19 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 27 Dec 2023 14:03:18 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno CC: Chunfeng Yun , Conor Dooley , Matthias Brugger , "Mathias Nyman" , , , , , , Eddie Hung , Macpaul Lin Subject: [PATCH v4 3/3] arm64: dts: mediatek: mt8195: Add 'rx-fifo-depth' for cherry Date: Wed, 27 Dec 2023 14:03:16 +0800 Message-ID: <20231227060316.8539-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227060316.8539-1-chunfeng.yun@mediatek.com> References: <20231227060316.8539-1-chunfeng.yun@mediatek.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10-2.825800-8.000000 X-TMASE-MatchedRID: ZzsyKKMlPmWLwgJA7qJvFEf49ONH0RaSGSqdEmeD/nUQVRHC3B6FYFfe kLFvP8UVQt2470g7vecqScZQsLRFpNRvK63SVd6gQPrPw3WbUAtRnscLnNAC7BjQD3m2MCf73j3 TOgY19l5UK0FnzcPd0uKOmN63egZIr78SC5iivxwURSScn+QSXt0H8LFZNFG7CKFCmhdu5cWMli PzJGLy1pXHFyiI0uGzANmR3/AtY5RjyzFNloJjQSJjvR2uj1AQfnRrx7yt7dn7QvrLnS2+q5yUI XNmAxUvnsnNd1zv3CVpp55fZDlsr34cY/B7JqXaYZ1R7NXn0MdBmmCXcKyFFPqy+VVvqH2X X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10-2.825800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: F39E914BBC51F28300BA942E2DD319AEC74CE0379EF1859D1C1E66BF5D291F672000:8 X-MTK: N Add the quirk property "rx-fifo-depth" to work around Gen1 isoc-in transfer issue which send out unexpected ACK even after device already finished the burst transfer with a short patcket, specially for a 4K camera device. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chunfeng Yun --- v4: change property value, and put before supply add reviewed-by Angelo v3: change value according to binding v2: use 'rx-fifo-depth' property --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index dd5b89b73190..00fcde60300e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1183,6 +1183,7 @@ &xhci0 { status = "okay"; + rx-fifo-depth = <3072>; vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; @@ -1190,6 +1191,7 @@ &xhci1 { status = "okay"; + rx-fifo-depth = <3072>; vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; };