@@ -158,6 +158,27 @@ usbphy0: phy@7b000 {
status = "disabled";
};
+ ssuniphy0: ssuniphy@4b0000 {
+ compatible = "qcom,ipq5332-usb-ssphy";
+ reg = <0x4b0000 0x800>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb_pcie_wrapper_pipe_clk";
+
+ clock-names = "pipe",
+ "phy_cfg_ahb",
+ "phy_ahb";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>;
+ reset-names = "por_rst";
+ #phy-cells = <0>;
+ qcom,phy-mux-sel = <&tcsr 0x10540 0x1>;
+ status = "disabled";
+ };
+
qfprom: efuse@a4000 {
compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x721>;
@@ -313,30 +334,34 @@ usb: usb@8a00000 {
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SNOC_USB_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_LFPS_CLK>;
+
clock-names = "core",
"iface",
"sleep",
- "mock_utmi";
+ "mock_utmi",
+ "aux",
+ "lfps";
resets = <&gcc GCC_USB_BCR>;
- qcom,select-utmi-as-pipe-clk;
-
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
- usb2_0_dwc: usb@8a00000 {
+ usb3_0_dwc: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x08a00000 0xe000>;
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- phy-names = "usb2-phy";
- phys = <&usbphy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usbphy0>, <&ssuniphy0>;
+
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
Add SS UNIPHY and update controller node for USB3. Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> --- This patch depends on the below series which adds support for USB2 in IPQ5332 https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 39 ++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 7 deletions(-)