@@ -800,6 +800,16 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+ /*
+ * Some ULPI USB PHY does not support internal VBUS supply, to drive
+ * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
+ * bit of OTG_CTRL register. Controller configures the USB2 PHY
+ * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
+ * with an external supply.
+ */
+ if (dwc->ulpi_ext_vbus_drv)
+ reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
+
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
return 0;
@@ -1553,6 +1563,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,dis-tx-ipgap-linecheck-quirk");
dwc->resume_hs_terminations = device_property_read_bool(dev,
"snps,resume-hs-terminations");
+ dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
+ "snps,ulpi-ext-vbus-drv");
dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
"snps,parkmode-disable-ss-quirk");
dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
@@ -280,6 +280,7 @@
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
+#define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17)
#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
@@ -1100,6 +1101,8 @@ struct dwc3_scratchpad_array {
* check during HS transmit.
* @resume-hs-terminations: Set if we enable quirk for fixing improper crc
* generation after resume from suspend.
+ * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
+ * VBUS with an external supply.
* @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
* instances in park mode.
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
@@ -1316,6 +1319,7 @@ struct dwc3 {
unsigned dis_del_phy_power_chg_quirk:1;
unsigned dis_tx_ipgap_linecheck_quirk:1;
unsigned resume_hs_terminations:1;
+ unsigned ulpi_ext_vbus_drv:1;
unsigned parkmode_disable_ss_quirk:1;
unsigned gfladj_refclk_lpm_sel:1;
Some ULPI USB PHY does not support internal VBUS supply, to drive the CPEN pin, which requires the configuration of the ULPI DRVVBUSEXTERNAL bit of OTG_CTRL register. Added 'snps,ulpi-ext-vbus-drv' a DT property to configure the USB2 PHY to drive VBUS with an external supply, by setting the USB2 PHY ULPIEXTVBUSDRV bit[:17] of the GUSB2PHYCFG register to drive VBUS with an external supply. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> --- drivers/usb/dwc3/core.c | 12 ++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 16 insertions(+)